Microchip Technology megaAVR 0 Series Manual page 54

returning from interrupts) and RET (when returning from subroutine calls) and the SP is incremented by
two.
The SP is decremented by '1' when data is pushed on the stack with the PUSH instruction, and
incremented by '1' when data is popped off the stack using the POP instruction.
To prevent corruption when updating the Stack Pointer from software, a write to SPL will automatically
disable interrupts for up to four instructions or until the next I/O memory write.
7.5.5 Register File
The register file consists of 32 8-bit general purpose working registers with single clock cycle access time.
The register file supports the following input/output schemes:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit Address Register Pointers for data space addressing,
enabling efficient address calculations.
Figure 7-4. AVR CPU General Purpose Working Registers
The register file is located in a separate address space and is, therefore, not accessible through
instructions operation on data memory.
7.5.5.1 The X-, Y-, and Z-Registers
Registers R26...R31 have added functions besides their general purpose usage.
These registers can form 16-bit Address Pointers for addressing data memory. These three address
registers are called the X-register, Y-register, and Z-register. Load and store instructions can use all X-,
Y-, and Z-registers, while the LPM and SPM instructions can only use the Z-register. Indirect calls and
jumps (ICALL and IJMP ) also use the Z-register.
Refer to the instruction set or Instruction Set Summary for more information about how the X-, Y-, and Z-
registers are used.
©
2018 Microchip Technology Inc.
0
7
R0
R1
R2
...
R13
R14
R15
R16
R17
...
R26
R27
R28
R29
R30
R31
Datasheet Preliminary
megaAVR
Addr.
0x00
0x01
0x02
0x0D
0x0E
0x0F
0x10
0x11
0x1A X-register Low Byte
0x1B X-register High Byte
0x1C Y-register Low Byte
0x1D Y-register High Byte
0x1E Z-register Low Byte
0x1F Z-register High Byte
®
0-Series
AVR CPU
DS40002015A-page 54