Microchip Technology megaAVR 0 Series Manual page 140

Interrupt Type
BOTHEDGES
RISING
FALLING
LEVEL
15.3.2.3 Virtual Ports
The Virtual PORT registers map the most frequently used regular PORT registers into the bit-accessible
I/O space. Writing to the Virtual PORT registers has the same effect as writing to the regular registers, but
allows for memory-specific instructions, such as bit-manipulation instructions, which are not valid for the
extended I/O memory space where the regular PORT registers reside.
Table 15-1. Virtual Port Mapping
Regular PORT Register
PORT.DIR
PORT.OUT
PORT.IN
PORT.INTFLAG
15.3.2.4 Peripheral Override
Peripherals such as USARTs and timers may be connected to I/O pins. Such peripherals will usually have
a primary and optionally also alternate I/O pin connection, selectable by PORTMUX. By configuring and
enabling such peripherals, the general-purpose I/O pin behavior normally controlled by PORT will be
overridden by the peripheral in a peripheral-dependent way. Some peripherals may not override all of the
PORT registers, leaving the PORT module to control some aspects of the I/O pin operation. Refer to the
description of each peripheral for information on the peripheral override. Any pin in a PORT which is not
overridden by a peripheral will continue to operate as a general-purpose I/O pin.
15.3.3 Interrupts
Table 15-2. Available Interrupt Vectors and Sources
Name Vector Description Conditions
PORTx PORT interrupt
Each PORT pin n can be configured as an interrupt source. Each interrupt can be individually enabled or
disabled by writing to ISC in PORTx.PINnCTRL.
When an interrupt condition occurs, the corresponding Interrupt Flag is set in the Interrupt Flags register
of the peripheral (peripheral.INTFLAGS).
An interrupt request is generated when the corresponding interrupt source is enabled and the Interrupt
Flag is set. The interrupt request remains active until the Interrupt Flag is cleared. See the peripheral's
INTFLAGS register for details on how to clear Interrupt Flags.
©
2018 Microchip Technology Inc.
Fully Asynchronous Pins
Will wake system
Will wake system
Will wake system
Will wake system
INTn in PORTx.INTFLAGS is raised as configured by ISC bit in
PORTx.PINnCTRL.
Datasheet Preliminary
megaAVR
I/O Pin Configuration (PORT)
Other Pins
Will wake system
Will not wake system
Will not wake system
Will wake system
Mapped to Virtual PORT Register
VPORT.DIR
VPORT.OUT
VPORT.IN
VPORT.INTFLAG
®
0-Series
DS40002015A-page 140