Microchip Technology megaAVR 0 Series Manual page 263

21.12.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7
RUNSTDBY
Access R/W
Reset 0
Bit 7 – RUNSTDBY Run in Standby
Value Description
0 RTC disabled in Standby sleep mode
1 RTC enabled in Standby sleep mode
Bits 6:3 – PRESCALER[3:0] Prescaler
These bits define the prescaling of the CLK_RTC clock signal. Due to synchronization between the RTC
clock and system clock domains, there is a latency of two RTC clock cycles from updating the register
until this has an effect. Application software needs to check that the CTRLABUSY flag in RTC.STATUS is
cleared before writing to this register.
Value Name
0x0 DIV1
0x1 DIV2
0x2 DIV4
0x3 DIV8
0x4 DIV16
0x5 DIV32
0x6 DIV64
0x7 DIV128
0x8 DIV256
0x9 DIV512
0xA DIV1024
0xB DIV2048
0xC DIV4096
0xD DIV8192
0xE DIV16384
0xF DIV32768
Bit 2 – CORREN Correction Enable
Value Description
0 Correction is disabled
1 Correction is enabled
Bit 0 – RTCEN RTC Enable
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2018 Microchip Technology Inc.
6 5
PRESCALER[3:0]
R/W R/W
0 0
Description
RTC clock/1 (no prescaling)
RTC clock/2
RTC clock/4
RTC clock/8
RTC clock/16
RTC clock/32
RTC clock/64
RTC clock/128
RTC clock/256
RTC clock/512
RTC clock/1024
RTC clock/2048
RTC clock/4096
RTC clock/8192
RTC clock/16384
RTC clock/32768
4 3
CORREN
R/W R/W
0 0
Datasheet Preliminary
®
megaAVR 0-Series
Real-Time Counter (RTC)
2 1
R/W
0
DS40002015A-page 263
0
RTCEN
R/W
0