Two-Wire Interface (Twi); Features; Overview - Microchip Technology megaAVR 0 Series Manual

24.

Two-Wire Interface (TWI)

24.1

Features

• Bidirectional, Two-Wire Communication Interface
2
• Philips I
– Standard-mode (Sm / 100 kHz with Slew-Rate Limited Output)
– Fast-mode (Fm / 400 kHz with Slew-Rate Limited Output)
– Fast-mode Plus (Fm+ / 1 MHz with ×10 Output Drive Strength)
• System Management Bus (SMBus) compatible (100 kHz with Slew-Rate Limited Output)
– Support Arbitration between Start/Repeated Start and Data Bit
– Slave Arbitration allows support for the Address Resolution Protocol (ARP)
– Configurable SMBus Layer 1 Timeouts in Hardware
– Independent Timeouts for Dual Mode
• Independent Master and Slave Operation
– Combined (same pins) or Dual Mode (separate pins)
– Single or Multi-Master Bus Operation with Full Arbitration Support
• Flexible Slave Address Match Hardware operating in all Sleep Modes, including Power-Down
– 7-bit and General Call Address Recognition
– 10-bit Addressing Support in Collaboration with Software
– Address Mask Register allows Address Range Masking, alternatively it can be used as a
secondary Address Match
– Optional Software Address Recognition for Unlimited Number of Addresses
• Input Filter For Bus Noise Suppression
24.2

Overview

The Two-Wire Interface (TWI) peripheral is a bidirectional, two-wire communication interface peripheral.
The only external hardware needed to implement the bus are two pull-up resistors, one for each bus line.
TWI is Philips/NXP Inter-IC (I²C) v2.1 and v.3 and System Management Bus (SMBus) compatible, though
it does not include support for High-speed-mode (Hs) or Ultra-Fast-mode (UFm in revision v.6 of the I²C
specification).
Any device connected to the TWI bus can act as a master, a slave, or both. The master generates the
serial clock (SCL) and initiates data transactions by addressing one slave and telling whether it wants to
transmit or receive data. One TWI bus connects many slaves to one or several masters. An arbitration
scheme handles the case where more than one master tries to transmit data at the same time. The
mechanisms for resolving bus contention are inherent in the protocol standards.
The TWI peripheral supports concurrent master and slave functionality, which are implemented as
independent units with separate enabling and configuration. The master module supports multi-master
bus operation and arbitration. It also generates the serial clock (SCL) by using a baud rate generator
capable of generating the standard (Sm) and fast (Fm, Fm+) bus frequencies from 100 kHz up to 1 MHz.
A "smart mode" is added that can be enabled to auto-trigger operations and thus reduce software
complexity.
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2018 Microchip Technology Inc.
C compatible
Datasheet Preliminary
®
megaAVR 0-Series
Two-Wire Interface (TWI)
DS40002015A-page 334