Microchip Technology megaAVR 0 Series Manual page 372

25.3.2.1 Checksum
The pre-calculated checksum must be present in the last location of the section to be checked. If the
BOOT section should be checked, the checksum must be saved in the last bytes of the BOOT section,
and similarly for APPLICATION and entire Flash.
be stored for the different sections. Also, see the CRCSCAN.CTRLB register description for how to
configure which section to check and the device fuse description for how to configure the BOOTEND and
APPEND fuses.
Table 25-1. Placement the Pre-Calculated Checksum in Flash
Section to Check
BOOT
BOOT and APPLICATION
Full Flash
25.3.3 Interrupts
Table 25-2. Available Interrupt Vectors and Sources
Name Vector Description
NMI Non-Maskable Interrupt
When the interrupt condition occurs, the OK flag in the Status register (CRCSCAN.STATUS) is cleared to
'0'.
An interrupt is enabled by writing a '1' to the respective Enable bit (NMIEN) in the Control A register
(CRCSCAN.CTRLA), but can only be disabled with a system Reset. An NMI is generated when the OK
flag in CRCSCAN.STATUS is cleared and the NMIEN bit is '1'. The NMI request remains active until a
system Reset, and cannot be disabled.
A non-maskable interrupt can be triggered even if interrupts are not globally enabled.
25.3.4 Sleep Mode Operation
CTCSCAN is halted in all sleep modes. In all CPU Sleep modes, the CRCSCAN peripheral is halted and
will resume operation when the CPU wakes up.
The CRCSCAN starts operation three cycles after writing the EN bit in CRCSCAN.CTRLA. During these
three cycles, it is possible to enter Sleep mode. In this case:
1. The CRCSCAN will not start until the CPU is woken up.
2. Any interrupt handler will execute after CRCSCAN has finished.
25.3.5 Debug Operation
Whenever the debugger accesses the device, for instance, reading or writing a peripheral or memory
location, the CRCSCAN peripheral will be disabled.
If the CRCSCAN is busy when the debugger accesses the device, the CRCSCAN will restart the ongoing
operation when the debugger accesses an internal register or when the debugger disconnects.
The BUSY bit in the Status register (CRCSCAN.STATUS) will read '1' if the CRCSCAN was busy when
the debugger caused it to disable, but it will not actively check any section as long as the debugger keeps
it disabled. There are synchronized CRC Status bits in the debugger's internal register space, which can
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2018 Microchip Technology Inc.
Cyclic Redundancy Check Memory Scan (CRCSCAN...
Table 25-1
CHECKSUM[15:8]
FUSE_BOOTEND*256-2
FUSE_APPEND*256-2
FLASHEND-1
Conditions
Generated on CRC failure
Datasheet Preliminary
megaAVR
shows explicitly how the checksum should
CHECKSUM[7:0]
FUSE_BOOTEND*256-1
FUSE_APPEND*256-1
FLASHEND
®
0-Series
DS40002015A-page 372