Microchip Technology Microsemi Hello FPGA Libero Design User Manual
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Microchip Technology Microsemi Hello FPGA Libero Design User Manual

Microchip Technology Microsemi Hello FPGA Libero Design User Manual

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UG0891
User Guide
Hello FPGA Libero Design

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Summary of Contents for Microchip Technology Microsemi Hello FPGA Libero Design

  • Page 1 UG0891 User Guide Hello FPGA Libero Design...
  • Page 2 About Microsemi ©2019 Microsemi, a wholly owned Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of subsidiary of Microchip Technology Inc. All semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets.

  • Page 3: Table Of Contents

    Contents 1 Revision History ........... . . 1 Revision 1.0 .
  • Page 4 Figures Figure 1 Hello FPGA Kit ..............3 Figure 2 LCD and Camera Sensor Boards .
  • Page 5 Tables Table 1 Resource Utilization ............12 Table 2 Resource Utilization .

  • Page 6: Revision History

    Revision History Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. Revision 1.0 This is the first publication of the document. Microsemi Proprietary UG0891 Revision 1.0...

  • Page 7: Hello Fpga

    Hello FPGA Hello FPGA Hello FPGA is a low cost, compact-sized, and a feature-rich FPGA kit based on the non-volatile, Flash- based, and low-power SmartFusion2 SoC FPGA (M2S010) from Microchip. SmartFusion2 SoC FPGAs offer more resources in low density with a complete Microcontroller Subsystem that includes a 166 MHz ARM Cortex M3 processor with an Embedded Trace Macrocell (ETM) and Instruction Cache, embedded flash, and extensive peripherals including CAN, TSE, and USB.

  • Page 8: Figure 1 Hello Fpga Kit

    Hello FPGA Figure 1 • Hello FPGA Kit The Hello FPGA kit includes the LCD board and the camera sensor. These boards can be connected to the Hello FPGA kit as shown in Figure 2, page 3. Figure 2 • LCD and Camera Sensor Boards Microsemi Proprietary UG0891 Revision 1.0...

  • Page 9: Video Demo Design

    Video Demo Design Video Demo Design The following figure shows the top-level video demo design in Libero. Figure 3 • Top-Level Hardware Implementation (Video Demo) The video demo design interfaces the Camera Sensor OV7725 and LCD with the SmartFusion2 SoC FPGA.

  • Page 10: Write_Lsram_0

    Video Demo Design Figure 4 • Line_write_read SD The Line_write_read module contains the following components: • WRITE_LSRAM_0, page 5 • Image Enhancement, page 5 • LCD_FSM, page 5 3.1.1 WRITE_LSRAM_0 Signals from the Camera PLK_I, H_REF, and DATA_I(8) are transferred through the Double Flip-Flop synchronizer circuit to ensure the integrity of these signals.

  • Page 11: Flashfreeze_Sb Module

    Video Demo Design FlashFreeze_SB Module Figure 5, page 6 shows the components of the FlashFreeze_SB_MSS module. The FlashFreeze_SB_MSS module configures the Microcontroller Sub System (MSS). The I2C peripheral in MSS is used to configure camera registers. MSS is the APB master which is connected to the APB slave (apb3_if) module to initialize LCD registers during startup.

  • Page 12: Ccc Ip

    Video Demo Design 3.2.1 CCC IP CCC IP is available in Libero SoC -> Clock and Management IP catalog. CCC IP acquires the 25/50 MHZ clock from the on-chip oscillator IP and generates the GL0 clock of 100 MHz and GL1 of 24 MHz clock.

  • Page 13: Mss Ip

    Video Demo Design 3.2.3 MSS IP SmartFusion2 Microcontroller Subsystem (MSS) IP is available in Libero SoC -> Catalog -> Processors. The MSS Component Configurator represents a graphical block diagram of the SmartFusion2 Microcontroller Subsystem. Each of MSS sub-blocks can be enabled or disabled as per the application requirements.

  • Page 14: Uart_Interface

    Video Demo Design UART_interface Figure 9 • UART_interface SD UART_interface SmartDesign performs the task of communication between the SmartFusion2 FPGA and the PC with PIC microcontroller as a bridge. Based on the data from Hello_FPGA GUI, receive_data module generates the address and the data. Addr_decoder module generates the values of brightness, contrast, and color and provides it to the Image_enchancement module.

  • Page 15: Apb3_If (Apb Slave)

    Video Demo Design APB3_if (APB slave) Figure 11 • Apb3_if Apb3_if module implements the APB slave Interface to communicate with APB3 Master (MSS). LCD initialization is done through this module based on the control and data words provided by the MSS. After LCD initialization, MSS gives the command to the APB slave to generate init_done signal.

  • Page 16: Ff_Generator

    Video Demo Design FF_GENERATOR Figure 14 • FF_Generator Module FF_Generator module implements a power down signal for the camera module based on the flash freeze signal FF_to_start_i, which indicates the fabric is in flash freeze or active. OSC_C0 IP OSC_C0 IP is available in the Libero SoC clock and management IP catalog. There are three oscillator blocks in the SmartFusion2 device that can be used in different use models: •...

  • Page 17: Resource Utilization

    Video Demo Design Resource Utilization The following table lists the resource utilization of the Video demo design. Table 1 • Resource Utilization Type Used Total Percentage 4LUT 12084 4.62 12084 4.83 User I/O 26.81 (single-ended) RAM1K18 4.76 MACC 13.64 Microsemi Proprietary UG0891 Revision 1.0...

  • Page 18: Digit Recognition (Ai) Demo Design

    Digit Recognition (AI) Demo Design Digit Recognition (AI) Demo Design The following figure shows the top-level AI digit recognition demo design in Libero. Figure 16 • Top-Level Hardware Implementation (AI Digit Recognition) AI Digit Recognition libero project aims to show Artificial Intelligence (AI) application. The Libero design for AI digit recognition is similar to the Video Demo Libero project with below additional modules.

  • Page 19: Flashfreeze Smartdesign

    Digit Recognition (AI) Demo Design FlashFreeze SmartDesign Figure 17 • FlashFreeze_SB FlashFreeze_SB_MSS configures the MSS. The I2C peripheral in MSS is used to configure camera registers. MSS is the APB master which is connected to the APB slave (apb3_if) module to initialize LCD registers during startup.

  • Page 20: Apb3_If (Apb Slave)

    Digit Recognition (AI) Demo Design Apb3_if (APB slave) Apb3_if is an APB slave module that communicates with the MSS. MSS first loads the weights into the Convolution Neural Network (CNN) SD through APB slave. After loading weights, MSS initializes the LCD display and transfers the LCD control to the FPGA fabric through init_done signal.

  • Page 21: Line_Write_Read Smartdesign

    Digit Recognition (AI) Demo Design Line_write_read SmartDesign Figure 19 • Line_write_read SD Line write read SmartDesign displays three images on the LCD: Image from camera. Image from camera in the scalable of size 28x28 at top left corner of LCD. Recognized digit of size 80x80 at left bottom corner.

  • Page 22: Resource Utilization

    Digit Recognition (AI) Demo Design camera is not pointing to a digit, the network will still output a digit that has the maximum value from the fully connected layer. Resource Utilization The following table lists the resource utilization of the digit recognition demo design. Table 2 •...

  • Page 23: Dsp (Fir) Filter Demo Design

    DSP (FIR) Filter Demo Design DSP (FIR) Filter Demo Design In this DSP FIR filter demo design, the FIR filter is implemented in the fabric for Low pass, High pass, Band pass, and Band reject filtering operations. The host interface is implemented in the fabric to communicate with the host PC.

  • Page 24: Flashfreeze_Sb_0 Module

    DSP (FIR) Filter Demo Design Figure 22 shows the top-level DSP FIR_LCD_FF demo design in Libero. Figure 22 • Top-Level DSP Design The Top module contains the following modules: • FlashFreeze_SB_0 Module • FIR_FILTER_0 Module • LCD_DISPLAY_0 Module FlashFreeze_SB_0 Module The FlashFreeze_SB_MSS module configures the Microcontroller Subsystem (MSS).

  • Page 25: Fir_Filter_0 Module

    DSP (FIR) Filter Demo Design Figure 23 • FlashFreeze_SB_0 FIR_FILTER_0 Module The FIR_FILTER_0 module implements the user logic in the fabric. This module implements the following finite-state machines: • Data Handling: Implements and controls operations like loading the filter input data to the corresponding input data buffer and loading filter coefficients to the corresponding coefficient memory buffers.

  • Page 26: Lcd_Display_0 Module

    DSP (FIR) Filter Demo Design LCD_DISPLAY_0 Module The LCD_DISPLAY_0 module implements the following functionalities: • apb3_if: Apb3_if module implements the APB slave Interface to communicate with APB3 Master (MSS). LCD initialization is done through this module based on the control and data words provided by the MSS.

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