Microchip Technology PIC12F1501 Manual

Microchip Technology PIC12F1501 Manual

20-pin flash, 8-bit microcontrollers with xlp technology

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20-Pin Flash, 8-Bit Microcontrollers
High-Performance RISC CPU:
• C Compiler Optimized Architecture
• Only 49 Instructions
• Operating Speed:
- DC – 20 MHz clock input
- DC – 200 ns instruction cycle
• Interrupt Capability with Automatic Context
Saving
• 16-Level Deep Hardware Stack with Optional
Overflow/Underflow Reset
• Direct, Indirect and Relative Addressing modes:
- Two full 16-bit File Select Registers (FSRs)
- FSRs can read program and data memory
Flexible Oscillator Structure:
• 16 MHz Internal Oscillator Block:
- Factory calibrated to ±1%, typical
- Software selectable frequency range from
16 MHz to 31 kHz
• 31 kHz Low-Power Internal Oscillator
• Three External Clock modes up to 20 MHz
Special Microcontroller Features:
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF1508/9)
- 2.3V to 5.5V (PIC16F1508/9)
• Self-Programmable under Software Control
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Programmable Low-Power Brown-out Reset
(LPBOR)
• Extended Watchdog Timer (WDT):
- Programmable period from 1 ms to 256s
• Programmable Code Protection
• In-Circuit Serial Programming™ (ICSP™) via Two
Pins
• Enhanced Low-Voltage Programming (LVP)
• In-Circuit Debug (ICD) via Two Pins
• Power-Saving Sleep mode:
- Low-Power Sleep mode
- Low-Power BOR (LPBOR)
• Integrated Temperature Indicator
• 128 Bytes High-Endurance Flash
- 100,000 write Flash endurance (minimum)
Memory:
• Up to 8 Kwords Linear Program Memory
Addressing
• Up to 512 bytes Linear Data Memory Addressing
• High-Endurance Flash Data Memory (HEF)
- 128 bytes if nonvolatile data storage
- 100k erase/write cycles
 2011-2015 Microchip Technology Inc.
PIC16(L)F1508/9
with XLP Technology
eXtreme Low-Power (XLP)
Features(PIC16LF1508/9):
• Sleep Current:
- 20 nA @ 1.8V, typical
• Watchdog Timer Current:
- 260 nA @ 1.8V, typical
• Operating Current:
- 30 A/MHz @ 1.8V, typical
• Secondary Oscillator Current:
- 700 nA @ 32 kHz, 1.8V, typical
Peripheral Features:
• Analog-to-Digital Converter (ADC):
- 10-bit resolution
- 12 external channels
- Three internal channels:
- Fixed Voltage Reference
- Digital-to-Analog Converter (DAC)
- Temperature Indicator channel
- Auto acquisition capability
- Conversion available during Sleep
• 5-Bit Digital-to-Analog Converter (DAC):
- Output available externally
- Positive reference selection
- Internal connections to comparators and ADC
• Two Comparators:
- Rail-to-rail inputs
- Power mode control
- Software controllable hysteresis
• Voltage Reference:
- 1.024V Fixed Voltage Reference (FVR) with
1x, 2x and 4x Gain output levels
• 18 I/O Pins (1 Input-only Pin):
- High current sink/source 25 mA/25 mA
- Individually programmable weak pull-ups
- Individually programmable
Interrupt-on-Change (IOC) pins
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Four 10-bit PWM modules
• Master Synchronous Serial Port (MSSP) with SPI
2
and I
C with:
- 7-bit address masking
- SMBus/PMBus™ compatibility
DS40001609E-page 1

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  • Page 1 • Up to 512 bytes Linear Data Memory Addressing and I C with: • High-Endurance Flash Data Memory (HEF) - 7-bit address masking - 128 bytes if nonvolatile data storage - SMBus/PMBus™ compatibility - 100k erase/write cycles  2011-2015 Microchip Technology Inc. DS40001609E-page 1...
  • Page 2 PIC16(L)F1507 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers. DS40001609 PIC16(L)F1508/9 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers. For other small form-factor package availability and marking information, please visit Note: or contact your local sales office. http://www.microchip.com/packaging  2011-2015 Microchip Technology Inc. DS40001609E-page 2...
  • Page 3 20-pin QFN, UQFN RA1/ICSPCLK MCLR/V /RA3 PIC16(L)F1508 PIC16(L)F1509 9 10 Note 1: See Table 1 for location of all peripheral functions. 2: It is recommended that the exposed bottom pad be connected to V  2011-2015 Microchip Technology Inc. DS40001609E-page 3...
  • Page 4 — — — — — — — — — — — — — — — — — — — — — (Register 11-1) Alternate pin function selected with the APFCON register. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 4...
  • Page 5: Table Of Contents

    31.0 Development Support................................380 32.0 Packaging Information................................384 Appendix A: Data Sheet Revision History............................397 The Microchip Website ..................................398 Customer Change Notification Service .............................. 398 Customer Support ....................................398 Product Identification System ................................399  2011-2015 Microchip Technology Inc. DS40001609E-page 5...
  • Page 6 When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at to receive the most current information on all of our products. www.microchip.com  2011-2015 Microchip Technology Inc. DS40001609E-page 6...
  • Page 7: Device Overview

    ● ● PWM3 ● ● ● ● ● PWM4 ● ● ● ● ● Timers Timer0 ● ● ● ● ● Timer1 ● ● ● ● ● Timer2 ● ● ● ● ●  2011-2015 Microchip Technology Inc. DS40001609E-page 8...
  • Page 8 TMR0 Indicator 10-bit CWG1 NCO1 CLC4 CLC3 CLC2 CLC1 PWM4 PWM3 PWM2 PWM1 EUSART See applicable chapters for more information on peripherals. Note 1: Table 1-1 for peripherals on specific devices. Figure 2-1.  2011-2015 Microchip Technology Inc. DS40001609E-page 9...
  • Page 9 = Schmitt Trigger input with CMOS levels I = Schmitt Trigger input with I HV = High Voltage XTAL = Crystal levels Alternate pin function selected with the APFCON (Register 11-1) register. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 10...
  • Page 10 = Schmitt Trigger input with CMOS levels I = Schmitt Trigger input with I HV = High Voltage XTAL = Crystal levels Alternate pin function selected with the APFCON (Register 11-1) register. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 11...
  • Page 11 = Schmitt Trigger input with CMOS levels I = Schmitt Trigger input with I HV = High Voltage XTAL = Crystal levels Alternate pin function selected with the APFCON (Register 11-1) register. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 12...
  • Page 12: Enhanced Mid-Range Cpu

    Indirect Direct Addr Addr BSR Reg FSR0 Reg FSR1 Reg STATUS Reg Power-up Instruction Timer Decode and Power-on Control Reset Watchdog Timer CLKIN Timing Brown-out Generation CLKOUT Reset W Reg Internal Oscillator Block  2011-2015 Microchip Technology Inc. DS40001609E-page 13...
  • Page 13 Section 3.6 “Indirect Addressing” details. Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section for more details. 28.0 “Instruction Set Summary”  2011-2015 Microchip Technology Inc. DS40001609E-page 14...
  • Page 14: Memory Organization

    High-Endurance Flash Device Space (Words) Address Memory Address Range PIC16LF1508 4,096 0FFFh 0F80h-0FFFh PIC16F1508 PIC16LF1509 8,192 1FFFh 1F80h-1FFFh PIC16F1509 Note 1: High-endurance Flash applies to low byte of each address in the range.  2011-2015 Microchip Technology Inc. DS40001609E-page 15...
  • Page 15 Program Page 2 0800h Memory Page 1 17FFh 0FFFh 1800h Page 3 1000h Rollover to Page 0 1FFFh 2000h Rollover to Page 0 Rollover to Page 3 7FFFh Rollover to Page 1 7FFFh  2011-2015 Microchip Technology Inc. DS40001609E-page 16...
  • Page 16 If your code must remain portable MOVIW 0[FSR1] with previous generations of microcontrollers, then the ;THE PROGRAM MEMORY IS IN W BRW instruction is not available so the older table read method must be used.  2011-2015 Microchip Technology Inc. DS40001609E-page 17...
  • Page 17 FSR0H seven bits select the registers/RAM in that bank. x06h or x86h FSR1L x07h or x87h FSR1H x08h or x88h x09h or x89h WREG x0Ah or x8Ah PCLATH x0Bh or x8Bh INTCON  2011-2015 Microchip Technology Inc. DS40001609E-page 18...
  • Page 18 For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the Note 1: second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.  2011-2015 Microchip Technology Inc. DS40001609E-page 19...
  • Page 19 See Section for more information. 3.6.2 “Linear Data Memory” General Purpose RAM 3.3.4 COMMON RAM (80 bytes maximum) There are 16 bytes of common RAM accessible from all banks. Common RAM (16 bytes)  2011-2015 Microchip Technology Inc. DS40001609E-page 20...
  • Page 20 3.3.5 DEVICE MEMORY MAPS The memory maps for Bank 0 through Bank 31 are shown in the tables in this section. TABLE 3-3: PIC16(L)F1508 MEMORY MAP, BANK 0-7 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 000h...
  • Page 21 TABLE 3-4: PIC16(L)F1509 MEMORY MAP, BANK 0-7 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 000h 080h 100h 180h 200h 280h 300h 380h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers...
  • Page 22 TABLE 3-5: PIC16(L)F1508/9 MEMORY MAP, BANK 8-23 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 400h 480h 500h 580h 600h 680h 700h 780h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers...
  • Page 23 TABLE 3-6: PIC16(L)F1508/9 MEMORY MAP, BANK 24-31 BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31 C00h C80h D00h D80h E00h E80h F00h F80h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers...
  • Page 24 CLC3GLS3 F27h CLC4CON F28h CLC4POL F29h CLC4SEL0 F2Ah CLC4SEL1 F2Bh CLC4GLS0 F2Ch CLC4GLS1 F2Dh CLC4GLS2 F2Eh CLC4GLS3 F2Fh F30h Unimplemented Read as ‘0’ F6Fh = Unimplemented data memory locations, read as ‘0’. Legend:  2011-2015 Microchip Technology Inc. DS40001609E-page 25...
  • Page 25 0000 0000 0000 0000 x8Bh x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Legend: Shaded locations are unimplemented, read as ‘0’.  2011-2015 Microchip Technology Inc. DS40001609E-page 26...
  • Page 26 = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Legend: PIC16F1508/9 only. Note Unimplemented, read as ‘1’.  2011-2015 Microchip Technology Inc. DS40001609E-page 27...
  • Page 27 = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Legend: PIC16F1508/9 only. Note Unimplemented, read as ‘1’.  2011-2015 Microchip Technology Inc. DS40001609E-page 28...
  • Page 28 = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Legend: PIC16F1508/9 only. Note Unimplemented, read as ‘1’.  2011-2015 Microchip Technology Inc. DS40001609E-page 29...
  • Page 29 = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Legend: PIC16F1508/9 only. Note Unimplemented, read as ‘1’.  2011-2015 Microchip Technology Inc. DS40001609E-page 30...
  • Page 30 = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Legend: PIC16F1508/9 only. Note Unimplemented, read as ‘1’.  2011-2015 Microchip Technology Inc. DS40001609E-page 31...
  • Page 31 = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Legend: PIC16F1508/9 only. Note Unimplemented, read as ‘1’.  2011-2015 Microchip Technology Inc. DS40001609E-page 32...
  • Page 32 When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.  2011-2015 Microchip Technology Inc. DS40001609E-page 33...
  • Page 33 Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL register will 0x05 return the contents of stack address 0x04 0x0F. 0x03 0x02 0x01 0x00 Stack Reset Enabled TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F (STVREN = 1)  2011-2015 Microchip Technology Inc. DS40001609E-page 34...
  • Page 34 Program Counter and pop the stack. 0x09 0x08 0x07 TOSH:TOSL 0x06 Return Address STKPTR = 0x06 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address  2011-2015 Microchip Technology Inc. DS40001609E-page 35...
  • Page 35 The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory  2011-2015 Microchip Technology Inc. DS40001609E-page 36...
  • Page 36 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Address Range Program Flash Memory 0xFFFF 0x7FFF Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.  2011-2015 Microchip Technology Inc. DS40001609E-page 37...
  • Page 37 Direct Addressing Indirect Addressing From Opcode FSRxH FSRxL 0 0 0 Bank Select Location Select Bank Select Location Select 00000 00001 00010 11111 0x00 0x7F Bank 31 Bank 0 Bank 1 Bank 2  2011-2015 Microchip Technology Inc. DS40001609E-page 38...
  • Page 38 0 0 1 Location Select 0x8000 Location Select 0x0000 0x2000 0x020 Bank 0 0x06F 0x0A0 Bank 1 Program 0x0EF Flash 0x120 Memory Bank 2 (low 8 bits) 0x16F 0xF20 Bank 30 0x7FFF 0xFFFF 0xF6F 0x29AF  2011-2015 Microchip Technology Inc. DS40001609E-page 39...
  • Page 39: Device Configuration

    8007h and Configuration Word 2 at 8008h. The DEBUG bit in Configuration Words is Note: managed automatically device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.  2011-2015 Microchip Technology Inc. DS40001609E-page 40...
  • Page 40 WDTE<1:0>: Watchdog Timer Enable bits 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled  2011-2015 Microchip Technology Inc. DS40001609E-page 41...
  • Page 41 When FSCM is enabled, Two-Speed Start-up will be automatically enabled, regardless of the IESO bit value. Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. Once enabled, code-protect can only be disabled by bulk erasing the device.  2011-2015 Microchip Technology Inc. DS40001609E-page 42...
  • Page 42 The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.  2011-2015 Microchip Technology Inc. DS40001609E-page 43...
  • Page 43 See Section 10.4 “User ID, Device ID and Configuration for more information on accessing these Word Access” memory locations. For more information on checksum calculation, see the “PIC12(L)F1501/PIC16(L)F150X Memory Programming Specification” (DS41573).  2011-2015 Microchip Technology Inc. DS40001609E-page 44...
  • Page 44 PIC16LF1509 10 1110 000 x xxxx PIC16F1509 10 1101 010 x xxxx bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision (see Table under DEV<8:0> above).  2011-2015 Microchip Technology Inc. DS40001609E-page 45...
  • Page 45: Oscillator Module (With Fail-Safe Clock Monitor)

    16 LFINTOSC and HFINTOSC. (See Internal Oscillator MHz HFINTOSC Block, Figure 5-1). A wide selection of device clock frequencies may be derived from these two clock sources.  2011-2015 Microchip Technology Inc. DS40001609E-page 46...
  • Page 46 LFINTOSC 31 kHz to WDT, PWRT, and Oscillator other Peripherals 600 kHz to ADC and Oscillator other Peripherals * Available with more than one IRCF selection Note 1: Section 5.2.2.4 “Peripheral Clock Sources”.  2011-2015 Microchip Technology Inc. DS40001609E-page 47...
  • Page 47 EC mode has three power modes to select from through the F bits in the Configuration Words: • ECH – High-power, 4-20 MHz • ECM – Medium-power, 0.5-4 MHz • ECL – Low-power, 0-0.5 MHz  2011-2015 Microchip Technology Inc. DS40001609E-page 48...
  • Page 48 In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock • AN949, “Making Your Oscillator Work” Start-up mode can be selected (see Section (DS00949) 5.4 “Two-Speed Clock Start-up Mode”).  2011-2015 Microchip Technology Inc. DS40001609E-page 49...
  • Page 49 Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) • TB097, “Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288)  2011-2015 Microchip Technology Inc. DS40001609E-page 50...
  • Page 50 (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running. The High-Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value.  2011-2015 Microchip Technology Inc. DS40001609E-page 51...
  • Page 51 Clock switching time delays are shown in Table 5-3. Start-up delay specifications are located in Table 29-8, “Oscillator Parameters”.  2011-2015 Microchip Technology Inc. DS40001609E-page 52...
  • Page 52 System Clock Table 5-3, “Oscillator Switching Delays” for more information. Note 1: LFINTOSC will continue to run if a peripheral has selected it as the clock source. See Section 5.2.2.4 “Peripheral Clock Sources”.  2011-2015 Microchip Technology Inc. DS40001609E-page 53...
  • Page 53 SOSCR bit is set, the SCS bits can be configured to the OSTS bit should be set, OSTS = 1, indicating the select the secondary oscillator. oscillator is stable and ready to be used.  2011-2015 Microchip Technology Inc. DS40001609E-page 54...
  • Page 54 Executing a SLEEP instruction will abort Note: the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear.  2011-2015 Microchip Technology Inc. DS40001609E-page 55...
  • Page 55 2 cycles LP, XT, HS 1024 Clock Cycles (OST) Secondary Oscillator 1024 Secondary Oscillator Cycles FIGURE 5-8: TWO-SPEED START-UP INTOSC OSC1 1022 1023 OSC2 Program Counter PC - N PC + 1 System Clock  2011-2015 Microchip Technology Inc. DS40001609E-page 56...
  • Page 56 The system clock will continue to be sourced from the Clear the OSFIF bit in the PIR2 register. internal clock source until the fail-safe condition has been cleared, see Section 5.5.3 “Fail-Safe Condition Clearing”.  2011-2015 Microchip Technology Inc. DS40001609E-page 57...
  • Page 57 Clock Monitor Output Failure Detected OSFIF Test Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in Note: this example have been chosen for clarity.  2011-2015 Microchip Technology Inc. DS40001609E-page 58...
  • Page 58 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Secondary oscillator 00 = Clock determined by FOSC<2:0> in Configuration Words. Duplicate frequency derived from HFINTOSC. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 59...
  • Page 59 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC 16 MHz Oscillator is stable and is driving the INTOSC 0 = HFINTOSC 16 MHz is not stable, the Start-up Oscillator is driving INTOSC  2011-2015 Microchip Technology Inc. DS40001609E-page 60...
  • Page 60 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> — CONFIG1 MCLRE PWRTE WDTE<1:0> FOSC<2:0> — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Legend:  2011-2015 Microchip Technology Inc. DS40001609E-page 61...
  • Page 61: Resets

    ICSP™ Programming Mode Exit RESET Instruction Stack Underflow Stack Overlfow MCLRE /MCLR Sleep Time-out Device Reset Power-on Reset Active Brown-out Power-up Reset Timer LFINTOSC PWRTE LPBOR Reset Table 6-1 for BOR active conditions. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 62...
  • Page 62 ‘10’, the BOR is on, except in Sleep. The BORRDY bit of the BORCON register. device start-up will be delayed until the BOR is ready BOR protection is unchanged by Sleep. and V is higher than the BOR threshold.  2011-2015 Microchip Technology Inc. DS40001609E-page 63...
  • Page 63 0 BORRDY: Brown-Out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive BOREN<1:0> bits are located in Configuration Words. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 64...
  • Page 64 Figure 6-3). This is useful for testing purposes or to software control. See Section 11.3 “PORTA Regis- synchronize more than one device operating in parallel. for more information. ters”  2011-2015 Microchip Technology Inc. DS40001609E-page 65...
  • Page 65 External Oscillators , PWRTEN = 0, IESO = 1 External Oscillators , PWRTEN = 1, IESO = 1 Note 1: Code execution begins 10 F cycles after the F clock is released.  2011-2015 Microchip Technology Inc. DS40001609E-page 66...
  • Page 66 Note 1: When the wake-up is due to an interrupt and the Global Interrupt Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.  2011-2015 Microchip Technology Inc. DS40001609E-page 67...
  • Page 67 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-Out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)  2011-2015 Microchip Technology Inc. DS40001609E-page 68...
  • Page 68 WDTE<1:0> FOSC<2:0> 13:8 — — — LPBOR BORV STVREN — CONFIG2 — — — — — — WRT<1:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.  2011-2015 Microchip Technology Inc. DS40001609E-page 69...
  • Page 69: Interrupts

    A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: INTERRUPT LOGIC Rev. 10-000010A 1/13/2014 TMR0IF Wake-up TMR0IE (If in Sleep mode) INTF Peripheral Interrupts INTE (TMR1IF) PIR1<0> IOCIF Interrupt (TMR1IE) PIE1<0> IOCIE to CPU PEIE PIRn<7> PIEn<7>  2011-2015 Microchip Technology Inc. DS40001609E-page 70...
  • Page 70 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.  2011-2015 Microchip Technology Inc. DS40001609E-page 71...
  • Page 71 Inst(PC) Inst(0004h) Interrupt PC-1 FSR ADDR PC+1 PC+2 0004h 0005h Execute 3-Cycle Instruction at PC INST(PC) Inst(0004h) Inst(0005h) Interrupt PC-1 FSR ADDR PC+1 PC+2 0004h 0005h Execute 3-Cycle Instruction at PC INST(PC) Inst(0004h)  2011-2015 Microchip Technology Inc. DS40001609E-page 72...
  • Page 72 Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: For minimum width of INT pulse, refer to AC specifications in Section 29.0 “Electrical Specifications”. 4: INTF is enabled to be set any time during the Q4-Q1 cycles.  2011-2015 Microchip Technology Inc. DS40001609E-page 73...
  • Page 73 ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved.  2011-2015 Microchip Technology Inc. DS40001609E-page 74...
  • Page 74 2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. 3: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers have been cleared by software.  2011-2015 Microchip Technology Inc. DS40001609E-page 75...
  • Page 75 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt.  2011-2015 Microchip Technology Inc. DS40001609E-page 76...
  • Page 76 1 = Enables the NCO interrupt 0 = Disables the NCO interrupt bit 1-0 Unimplemented: Read as ‘0’ Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt.  2011-2015 Microchip Technology Inc. DS40001609E-page 77...
  • Page 77 CLC1IE: Configurable Logic Block 1 Interrupt Enable bit 1 = Enables the CLC 1 interrupt 0 = Disables the CLC 1 interrupt Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt.  2011-2015 Microchip Technology Inc. DS40001609E-page 78...
  • Page 78 Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2011-2015 Microchip Technology Inc. DS40001609E-page 79...
  • Page 79 Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2011-2015 Microchip Technology Inc. DS40001609E-page 80...
  • Page 80 Global Enable bit, GIE of the INTCON register. User software should ensure appropriate interrupt flag bits are clear prior to enabling an interrupt.  2011-2015 Microchip Technology Inc. DS40001609E-page 81...
  • Page 81 PIR2 OSFIF C2IF C1IF — BCL1IF NCO1IF — — PIR3 — — — — CLC4IF CLC3IF CLC2IF CLC1IF Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.  2011-2015 Microchip Technology Inc. DS40001609E-page 82...
  • Page 82: Power-Down Mode (Sleep)

    External Reset input on MCLR pin, if enabled BOR Reset, if enabled POR Reset Watchdog Timer, if enabled Any external interrupt Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information)  2011-2015 Microchip Technology Inc. DS40001609E-page 83...
  • Page 83 PIC16LF1508/9 is an unregulated device and is always in the lowest power state when in Sleep, with no wake-up time pen- alty. This device has a lower maximum voltage than PIC16F1508/9. Section 29.0 “Electrical Specifications” more information.  2011-2015 Microchip Technology Inc. DS40001609E-page 84...
  • Page 84 PIR3 — — — — CLC4IF CLC3IF CLC2IF CLC1IF STATUS — — — WDTCON — — WDTPS<4:0> SWDTEN Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.  2011-2015 Microchip Technology Inc. DS40001609E-page 85...
  • Page 85: Watchdog Timer (Wdt)

    • Multiple Reset conditions • Operation during Sleep FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM Rev. 10-000141A 7/30/2013 WDTE<1:0> = 01 SWDTEN 23- it Programmable WDTE<1:0> = 11 LFINTOSC Time-out Prescaler WDT WDTE<1:0> = 10 WDTPS<4:0> Sleep  2011-2015 Microchip Technology Inc. DS40001609E-page 86...
  • Page 86 Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) Unaffected  2011-2015 Microchip Technology Inc. DS40001609E-page 87...
  • Page 87 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 00: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 88...
  • Page 88 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> — CONFIG1 MCLRE PWRTE WDTE<1:0> FOSC<2:0> — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer. Legend:  2011-2015 Microchip Technology Inc. DS40001609E-page 89...
  • Page 89: Flash Program Memory Control

    PMADRH register and the LSB Write is written to the PMADRL register. Row Erase Device Latches (words) (words) 10.1.1 PMCON1 AND PMCON2 REGISTERS PIC16(L)F1508 PIC16(L)F1509 PMCON1 is the control register for Flash program memory accesses.  2011-2015 Microchip Technology Inc. DS40001609E-page 90...
  • Page 90 (RD = 1) 2-cycle instruction on the next instruction after the RD bit is set. Instruction fetched ignored NOP execution forced Instruction fetched ignored NOP execution forced Data read now in PMDATH:PMDATL Read Operation  2011-2015 Microchip Technology Inc. DS40001609E-page 91...
  • Page 91 10-2) ; Ignored (Figure 10-2) MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location  2011-2015 Microchip Technology Inc. DS40001609E-page 92...
  • Page 92 Instruction fetched ignored NOP execution forced instruction. Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. Unlock Sequence  2011-2015 Microchip Technology Inc. DS40001609E-page 93...
  • Page 93 (WREN = 1) Unlock Sequence (See Note 1) CPU stalls while Erase operation completes (2 ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) Erase Operation Note 1: See Figure 10-3.  2011-2015 Microchip Technology Inc. DS40001609E-page 94...
  • Page 94 ; NOP instructions are forced as processor starts ; row erase of program memory. ; The processor stalls until the erase process is complete ; after erase processor continues with 3rd instruction PMCON1,WREN ; Disable writes INTCON,GIE ; Enable interrupts  2011-2015 Microchip Technology Inc. DS40001609E-page 95...
  • Page 95 Unloaded latches will remain in the blank state. An example of the complete write sequence is shown in Example 10-3. The initial address is loaded into the PMADRH:PMADRL register pair; the data is loaded using indirect addressing.  2011-2015 Microchip Technology Inc. DS40001609E-page 96...
  • Page 96 FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES Rev. 10-000004A 7/30/2013 PMADRH PMADRL PMDATH PMDATL Program Memory Write Latches Write Latch #0 Write Latch #1 Write Latch #30 Write Latch #31 PMADRL<4:0> Addr Addr Addr Addr 000h 0000h 0001h...
  • Page 97 No delay when writing to Load Write Latches Only Disable Write/Erase (LWLO = 1) Program Memory Latches Operation (WREN = 0) Re-enable Interrupts (GIE = 1) Increment Address (PMADRH:PMADRL++) Write Operation Note 1: See Figure 10-3.  2011-2015 Microchip Technology Inc. DS40001609E-page 98...
  • Page 98 ; to program memory. ; After NOPs, the processor ; stalls until the self-write process in complete ; after write processor continues with 3rd instruction PMCON1,WREN ; Disable writes INTCON,GIE ; Enable interrupts  2011-2015 Microchip Technology Inc. DS40001609E-page 99...
  • Page 99 RAM image Erase Operation (See Note 2) Write Operation Use RAM image (See Note 3) Modify Operation Note 1: See Figure 10-2. 2: See Figure 10-4. 3: See Figure 10-5.  2011-2015 Microchip Technology Inc. DS40001609E-page 100...
  • Page 100 10-2) INTCON,GIE ; Restore interrupts MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location  2011-2015 Microchip Technology Inc. DS40001609E-page 101...
  • Page 101 Flash Program Memory Read Operation (See Note 1) PMDAT = RAM image ? Fail Verify Operation Last word ? Verify Operation Note 1: See Figure 10-2.  2011-2015 Microchip Technology Inc. DS40001609E-page 102...
  • Page 102 ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘1’ bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address Unimplemented, read as ‘1’. Note  2011-2015 Microchip Technology Inc. DS40001609E-page 103...
  • Page 103 The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1). The LWLO bit is ignored during a program memory erase operation (FREE = 1).  2011-2015 Microchip Technology Inc. DS40001609E-page 104...
  • Page 104 WDTE<1:0> FOSC<2:0> 13:8 — — — LPBOR BORV STVREN — CONFIG2 — — — — — — WRT<1:0> — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets. Legend:  2011-2015 Microchip Technology Inc. DS40001609E-page 105...
  • Page 105: I/O Ports

    A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 11-1.  2011-2015 Microchip Technology Inc. DS40001609E-page 106...
  • Page 106 1 = CLC1 function is on RC5 0 = CLC1 function is on RA2 bit 0 NCO1SEL: Pin Selection bit 1 = NCO1 function is on RC6 0 = NCO1 function is on RC1  2011-2015 Microchip Technology Inc. DS40001609E-page 107...
  • Page 107 BANKSEL PORTA CLRF PORTA ;Init PORTA BANKSEL LATA ;Data Latch CLRF LATA BANKSEL ANSELA CLRF ANSELA ;digital I/O BANKSEL TRISA MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA ;and set RA<2:0> as ;outputs  2011-2015 Microchip Technology Inc. DS40001609E-page 108...
  • Page 108 Unimplemented: Read as ‘1’ bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Unimplemented, read as ‘1’. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 109...
  • Page 109 0 = Digital I/O. Pin is assigned to port or digital special function. When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin.  2011-2015 Microchip Technology Inc. DS40001609E-page 110...
  • Page 110 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> — CONFIG1 FOSC<2:0> MCLRE PWRTE WDTE<1:0> — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. Legend:  2011-2015 Microchip Technology Inc. DS40001609E-page 111...
  • Page 111 The ANSELB bits default to the Analog Note: mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software.  2011-2015 Microchip Technology Inc. DS40001609E-page 112...
  • Page 112 ‘0’ = Bit is cleared bit 7-4 RB<7:4>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output bit 3-0 Unimplemented: Read as ‘0’  2011-2015 Microchip Technology Inc. DS40001609E-page 113...
  • Page 113 Unimplemented: Read as ‘0’ When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin.  2011-2015 Microchip Technology Inc. DS40001609E-page 114...
  • Page 114 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> — CONFIG1 FOSC<2:0> MCLRE PWRTE WDTE<1:0> — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTB. Legend:  2011-2015 Microchip Technology Inc. DS40001609E-page 115...
  • Page 115 The ANSELC bits default to the Analog Note: Alternate pin (see APFCON register). mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software.  2011-2015 Microchip Technology Inc. DS40001609E-page 116...
  • Page 116 ‘0’ = Bit is cleared bit 7-0 LATC<7:0>: PORTC Output Latch Value bits Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is Note 1: return of actual I/O pin values.  2011-2015 Microchip Technology Inc. DS40001609E-page 117...
  • Page 117 LATC1 LATC0 PORTC TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Legend:  2011-2015 Microchip Technology Inc. DS40001609E-page 118...
  • Page 118: Interrupt-On-Change

    Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCxF register will be updated prior to the first instruction executed out of Sleep.  2011-2015 Microchip Technology Inc. DS40001609E-page 119...
  • Page 119 Q4Q1 edge detect to data bus data bus = IOCAFx IOCAPx 0 or 1 write IOCAFx IOCIE IOC interrupt to CPU core from all other IOCnFx individual pin detectors Q4Q1 Q4Q1 Q4Q1 Q4Q1  2011-2015 Microchip Technology Inc. DS40001609E-page 120...
  • Page 120 Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was detected on RAx. 0 = No change was detected, or the user cleared the detected change.  2011-2015 Microchip Technology Inc. DS40001609E-page 121...
  • Page 121 Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change. bit 3-0 Unimplemented: Read as ‘0’  2011-2015 Microchip Technology Inc. DS40001609E-page 122...
  • Page 122 TRISA2 TRISA1 TRISA0 TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change. Legend: Unimplemented, read as ‘1’. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 123...
  • Page 123: Fixed Voltage Reference (Fvr)

    BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled. All PIC16F1508/9 devices, when The device runs off of the Low-Power Regulator when in Sleep VREGPM = 1 and not in Sleep mode.  2011-2015 Microchip Technology Inc. DS40001609E-page 124...
  • Page 124 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR>1:0> ADFVR<1:0> Shaded cells are unused by the Fixed Voltage Reference module. Legend:  2011-2015 Microchip Technology Inc. DS40001609E-page 125...
  • Page 125: Temperature Indicator Module

    200 s between sequential operate the circuit. The low range is provided for low conversions of the temperature indicator output. voltage operation.  2011-2015 Microchip Technology Inc. DS40001609E-page 126...
  • Page 126 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR>1:0> ADFVR<1:0> Shaded cells are unused by the temperature indicator module. Legend:  2011-2015 Microchip Technology Inc. DS40001609E-page 127...
  • Page 127: Analog-To-Digital Converter (Adc) Module

    Inputs FVR_buffer1 Sample Circuit CHS<4:0> ADFM set bit ADIF complete 10-bit Result Write to bit GO/DONE GO/DONE start ADRESH ADRESL Enable Trigger Select TRIGSEL<3:0> ADON . . . Trigger Sources AUTO CONVERSION TRIGGER  2011-2015 Microchip Technology Inc. DS40001609E-page 128...
  • Page 128 The positive voltage reference (ref+) is selected by the ADPREF bits in the ADCON1 register. The positive voltage reference source can be: • V + pin • V The negative voltage reference (ref-) source is: • V  2011-2015 Microchip Technology Inc. DS40001609E-page 129...
  • Page 129 (THCD). ADRESH:ADRESL is loaded, GO bit is cleared, Set GO bit ADIF bit is set, holding capacitor is reconnected to analog input. Enable ADC (ADON bit) Select channel (ACS bits)  2011-2015 Microchip Technology Inc. DS40001609E-page 130...
  • Page 130 7 bit 0 bit 7 bit 0 10-bit ADC Result Unimplemented: Read as ‘0’ (ADFM = 1) bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit ADC Result  2011-2015 Microchip Technology Inc. DS40001609E-page 131...
  • Page 131 SOURCES turned off and any pending conversion is Source Peripheral Signal Name terminated. Timer0 T0_overflow Timer1 T1_overflow Timer2 T2_match Comparator C1 C1OUT_sync Comparator C2 C2OUT_sync CLC1 LC1_out CLC2 LC2_out CLC3 LC3_out CLC4 LC4_out  2011-2015 Microchip Technology Inc. DS40001609E-page 132...
  • Page 132 Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 15.4 “ADC Acquisi- tion Requirements”.  2011-2015 Microchip Technology Inc. DS40001609E-page 133...
  • Page 133 0 = ADC is disabled and consumes no operating current for more information. Note 1: Section 14.0 “Temperature Indicator Module” for more information. Section 13.0 “Fixed Voltage Reference (FVR)” See Section 16.0 “5-Bit Digital-to-Analog Converter (DAC) Module” for more information.  2011-2015 Microchip Technology Inc. DS40001609E-page 134...
  • Page 134 11 = Reserved When selecting the V + pin as the source of the positive reference, be aware that a minimum voltage Note 1: specification exists. See for details. Section 29.0 “Electrical Specifications”  2011-2015 Microchip Technology Inc. DS40001609E-page 135...
  • Page 135 1101 = Reserved 1110 = Reserved 1111 = Reserved bit 3-0 Unimplemented: Read as ‘0’ This is a rising edge sensitive input for all sources. Note 1: Signal also sets its corresponding interrupt flag.  2011-2015 Microchip Technology Inc. DS40001609E-page 136...
  • Page 136 -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use.  2011-2015 Microchip Technology Inc. DS40001609E-page 137...
  • Page 137 -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result  2011-2015 Microchip Technology Inc. DS40001609E-page 138...
  • Page 138 2: The charge holding capacitor (C ) is not discharged after each conversion. HOLD 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.  2011-2015 Microchip Technology Inc. DS40001609E-page 139...
  • Page 139 Note 1: Refer to Section 29.0 “Electrical Specifications”. FIGURE 15-5: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh 3FCh 3FBh Analog Input Voltage 0.5 LSB 1.5 LSB Zero-Scale Ref- Full-Scale Transition Ref+ Transition  2011-2015 Microchip Technology Inc. DS40001609E-page 140...
  • Page 140 = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not Legend: used for ADC module. Unimplemented, read as ‘1’. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 141...
  • Page 141: 5-Bit Digital-To-Analog Converter (Dac) Module

    FIGURE 16-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Rev. 10-000026A 7/30/2013 SOURCE DACR<4:0> DACPSS DACEN DACx_output To Peripherals Steps DACxOUT1 DACOE1 DACxOUT2 DACOE2 SOURCE Note 1: The unbuffered DACx_output is provided on the DACxOUT pin(s).  2011-2015 Microchip Technology Inc. DS40001609E-page 142...
  • Page 142     DACR 4:0    DACx_output – -----------------------------  SOURCE SOURCE  SOURCE See the DACxCON0 register for the available V + and V - selections. Note: SOURCE SOURCE  2011-2015 Microchip Technology Inc. DS40001609E-page 143...
  • Page 143 DAC1CON0 DACEN — DACOE1 DACOE2 — DACPSS — — DAC1CON1 — — — DACR<4:0> — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module. Legend:  2011-2015 Microchip Technology Inc. DS40001609E-page 144...
  • Page 144: Comparator Module

    CxINTN Interrupt Falling CxIN2- Edge CxON CxIN3- CxVN CxOUT FVR_buffer2 MCxOUT CxVP CxIN+ DAC_out CxOUT_async CxSP CxHYS CxPOL FVR_buffer2 peripherals CxOUT_sync CxPCH<1:0> CxON peripherals CxSYNC CxOE TRIS bit CxOUT (From Timer1 Module) T1CLK  2011-2015 Microchip Technology Inc. DS40001609E-page 145...
  • Page 145 Configuring the CxPCH<1:0> bits of the CMxCON1 latched with each instruction cycle. register directs an internal voltage reference or an Unless otherwise specified, external analog pin to the non-inverting input of the comparator: outputs are not latched.  2011-2015 Microchip Technology Inc. DS40001609E-page 146...
  • Page 146 = Input Capacitance = Leakage Current at the pin due to various junctions LEAKAGE = Interconnect Resistance = Source Impedance = Analog Voltage = Threshold Voltage Note 1: See Section 29.0 “Electrical Specifications”.  2011-2015 Microchip Technology Inc. DS40001609E-page 147...
  • Page 147 • CxINTP bit of the CMxCON1 register (for a rising edge detection) • CxINTN bit of the CMxCON1 register (for a falling edge detection) • PEIE and GIE bits of the INTCON register  2011-2015 Microchip Technology Inc. DS40001609E-page 148...
  • Page 148 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous  2011-2015 Microchip Technology Inc. DS40001609E-page 149...
  • Page 149 -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit  2011-2015 Microchip Technology Inc. DS40001609E-page 150...
  • Page 150 — — TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module. Legend: Unimplemented, read as ‘1’. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 151...
  • Page 151: Timer0 Module

    TIMER0 BLOCK DIAGRAM Rev. 10-000017A TMR0CS 8/5/2013 Fosc/4 T0CKI T0_overflow T0CKI TMR0 Sync Circuit Prescaler write TMR0 TMR0SE set bit PS<2:0> TMR0IF Note 1: The T0CKI prescale output frequency should not exceed F  2011-2015 Microchip Technology Inc. DS40001609E-page 152...
  • Page 152 Section 29.0 “Electrical Specifications”. 18.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode.  2011-2015 Microchip Technology Inc. DS40001609E-page 153...
  • Page 153 TRISA5 TRISA4 TRISA2 TRISA1 TRISA0 — — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. Legend: Page provides register information. Unimplemented, read as ‘1’. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 154...
  • Page 154: Timer1 Module With Gate Control

    Input Secondary Clock To Clock Switching Module Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.  2011-2015 Microchip Technology Inc. DS40001609E-page 155...
  • Page 155 (TMR1ON=1) when T1CKI is low. TABLE 19-2: CLOCK SOURCE SELECTIONS TMR1CS<1:0> T1OSCEN Clock Source LFINTOSC Secondary Oscillator Circuit on SOSCI/SOSCO Pins External Clocking on T1CKI Pin System Clock (F Instruction Clock (F  2011-2015 Microchip Technology Inc. DS40001609E-page 156...
  • Page 156 (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads.  2011-2015 Microchip Technology Inc. DS40001609E-page 157...
  • Page 157 Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See Figure 19-6 for timing details.  2011-2015 Microchip Technology Inc. DS40001609E-page 158...
  • Page 158 T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2011-2015 Microchip Technology Inc. DS40001609E-page 159...
  • Page 159 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8  2011-2015 Microchip Technology Inc. DS40001609E-page 160...
  • Page 160 DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N + 1 N + 2 Cleared by Set by hardware on Cleared by software software TMR1GIF falling edge of T1GVAL  2011-2015 Microchip Technology Inc. DS40001609E-page 161...
  • Page 161 T1G t1g_in T1CKI T1GVAL Timer1 N + 1 N + 2 N + 3 N + 4 Set by hardware on Cleared by Cleared by software software falling edge of T1GVAL TMR1GIF  2011-2015 Microchip Technology Inc. DS40001609E-page 162...
  • Page 162 0 = Synchronize asynchronous clock input with system clock (F bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 and clears Timer1 gate flip-flop  2011-2015 Microchip Technology Inc. DS40001609E-page 163...
  • Page 163 T1GSS<1:0>: Timer1 Gate Source Select bits 11 = Comparator 2 optionally synchronized output (C2OUT_sync) 10 = Comparator 1 optionally synchronized output (C1OUT_sync) 01 = Timer0 overflow output (T0_overflow) 00 = Timer1 gate pin (T1G)  2011-2015 Microchip Technology Inc. DS40001609E-page 164...
  • Page 164 T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> DONE — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module. Legend: Page provides register information. Unimplemented, read as ‘1’. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 165...
  • Page 165: Timer2 Module

    TIMER2 TIMING DIAGRAM Rev. 10-000020A 7/30/2013 Prescale 0x03 0x00 0x01 0x02 0x03 0x00 0x01 0x02 TMR2 T2_match Pulse Width Note 1: The Pulse Width of T2_match is equal to the scaled input of TMR2.  2011-2015 Microchip Technology Inc. DS40001609E-page 166...
  • Page 166 Sleep mode. The contents of the TMR2 and PR2 inclusive) can be selected with the postscaler control registers will remain unchanged while the processor is bits, T2OUTPS<3:0>, of the T2CON register. in Sleep mode.  2011-2015 Microchip Technology Inc. DS40001609E-page 167...
  • Page 167 — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> TMR2 Holding Register for the 8-bit TMR2 Count 166* — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. Legend: Page provides register information.  2011-2015 Microchip Technology Inc. DS40001609E-page 168...
  • Page 168: Master Synchronous Serial Port (Mssp) Module

    Data bus Read Write SSPxBUF SSPxSR SDO_out Bit 0 Shift clock (CKP, CKE) clock select SSPM<3:0> Control Enable Edge enable (T2_match) SCK_out Edge Prescaler enable 4, 16, 64 Baud Rate TRIS bit Generator (SSPxADD)  2011-2015 Microchip Technology Inc. DS40001609E-page 169...
  • Page 169 Stop bit detected SCLx in Set/Reset: S, P, SSPxSTAT, Write collsion detect WCOL, SSPOV Clock arbitration Bus collision Reset SEN, PEN (SSPxCON2) State counter for end Set SSPxIF, BCLxIF of XMIT/RCV Address match detect  2011-2015 Microchip Technology Inc. DS40001609E-page 170...
  • Page 170 C™ SLAVE MODE) Rev. 10-000078A 7/30/2013 Internal data bus Read Write SSPxBUF SCLx Shift clock SDAx SSPxSR SSPxMSK Match detect Addr Match SSPxADD Start and Stop Set, Reset S, P bit Detect bits (SSPxSTAT)  2011-2015 Microchip Technology Inc. DS40001609E-page 171...
  • Page 171 The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register.  2011-2015 Microchip Technology Inc. DS40001609E-page 172...
  • Page 172 In receive operations, SSPxSR and SSPxBUF together create a buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set.  2011-2015 Microchip Technology Inc. DS40001609E-page 173...
  • Page 173 WCOL of the SSPxCON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully.  2011-2015 Microchip Technology Inc. DS40001609E-page 174...
  • Page 174 = 1010 SDOx SDIx Serial Input Buffer Serial Input Buffer (SSPxBUF) (SSPxBUF) SDIx SDOx Shift Register Shift Register (SSPxSR) (SSPxSR) Serial clock SCKx SCKx Slave Select General I/O Processor 1 (optional) Processor 2  2011-2015 Microchip Technology Inc. DS40001609E-page 175...
  • Page 175 (CKE = 1) SDIx (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDIx (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPxIF SSPxSR to SSPxBUF  2011-2015 Microchip Technology Inc. DS40001609E-page 176...
  • Page 176 When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SSx pin to a high level or clearing the SSPEN bit.  2011-2015 Microchip Technology Inc. DS40001609E-page 177...
  • Page 177 SSPxBUF to SSPxSR bit 6 bit 6 bit 7 bit 0 SDOx bit 7 SDIx bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF  2011-2015 Microchip Technology Inc. DS40001609E-page 178...
  • Page 178 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDOx bit 7 SDIx bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active  2011-2015 Microchip Technology Inc. DS40001609E-page 179...
  • Page 179 TRISC3 TRISC2 TRISC1 TRISC0 — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Legend: Page provides register information. Unimplemented, read as ‘1’. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 180...
  • Page 180  2011-2015 Microchip Technology Inc. DS40001609E-page 181...
  • Page 181 Arbitration usually occurs very rarely, but it is a neces- sary process for proper multi-master support.  2011-2015 Microchip Technology Inc. DS40001609E-page 182...
  • Page 182 Bus Collision Any time the SDAx line is sampled mum hold time and may help on buses with large low by the module while it is out- capacitance. putting and expected high state.  2011-2015 Microchip Technology Inc. DS40001609E-page 183...
  • Page 183 C START AND STOP CONDITIONS SDAx SCLx Change of Change of Data Allowed Data Allowed Start Stop Condition Condition FIGURE 21-13: C RESTART CONDITION Change of Change of Data Allowed Data Allowed Restart Condition  2011-2015 Microchip Technology Inc. DS40001609E-page 184...
  • Page 184 Section21.5.9 “SSPx for more information. for the MSSP module configured as an I C slave in Mask Register” 7-bit Addressing mode. Figure 21-14 Figure 21-15 are used as visual references for this description.  2011-2015 Microchip Technology Inc. DS40001609E-page 185...
  • Page 185 ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSPSTAT register.  2011-2015 Microchip Technology Inc. DS40001609E-page 186...
  • Page 186 PIC16(L)F1508/9 FIGURE 21-14: C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)  2011-2015 Microchip Technology Inc. DS40001609E-page 187...
  • Page 187 PIC16(L)F1508/9 FIGURE 21-15: C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)  2011-2015 Microchip Technology Inc. DS40001609E-page 188...
  • Page 188 PIC16(L)F1508/9 FIGURE 21-16: C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)  2011-2015 Microchip Technology Inc. DS40001609E-page 189...
  • Page 189 PIC16(L)F1508/9 FIGURE 21-17: C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)  2011-2015 Microchip Technology Inc. DS40001609E-page 190...
  • Page 190 16. The slave is no longer addressed. addressed again. User software can use the BCLxIF bit to handle a slave bus collision.  2011-2015 Microchip Technology Inc. DS40001609E-page 191...
  • Page 191 PIC16(L)F1508/9 FIGURE 21-18: C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)  2011-2015 Microchip Technology Inc. DS40001609E-page 192...
  • Page 192 Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCLx line to receive a Stop.  2011-2015 Microchip Technology Inc. DS40001609E-page 193...
  • Page 193 PIC16(L)F1508/9 FIGURE 21-19: C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)  2011-2015 Microchip Technology Inc. DS40001609E-page 194...
  • Page 194 16. Slave reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCLx. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission.  2011-2015 Microchip Technology Inc. DS40001609E-page 195...
  • Page 195 PIC16(L)F1508/9 FIGURE 21-20: C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)  2011-2015 Microchip Technology Inc. DS40001609E-page 196...
  • Page 196 PIC16(L)F1508/9 FIGURE 21-21: C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)  2011-2015 Microchip Technology Inc. DS40001609E-page 197...
  • Page 197 PIC16(L)F1508/9 FIGURE 21-22: C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)  2011-2015 Microchip Technology Inc. DS40001609E-page 198...
  • Page 198 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx – DX ‚ SCLx Master device asserts clock Master device releases clock SSPxCON1  2011-2015 Microchip Technology Inc. DS40001609E-page 199...
  • Page 199 • 7-bit Address mode: address compare of A<7:1>. • 10-bit Address mode: address compare of A<7:0> only. The SSPx mask has no effect during the reception of the first (high) byte of the address.  2011-2015 Microchip Technology Inc. DS40001609E-page 200...
  • Page 200 SSPxBUF did not occur 2: When in Master mode, Start/Stop detec- tion is masked and an interrupt is gener- ated when the SEN/PEN bit is cleared and the generation is complete.  2011-2015 Microchip Technology Inc. DS40001609E-page 201...
  • Page 201 WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not idle. Because queuing of events is not allowed, Note: writing to the lower five bits of SSPxCON2 is disabled until the Start condition is complete.  2011-2015 Microchip Technology Inc. DS40001609E-page 202...
  • Page 202 Write to SEN bit occurs here At completion of Start bit, SDAx = 1, hardware clears SEN bit SCLx = 1 and sets SSPxIF bit Write to SSPxBUF occurs here SDAx 1st bit 2nd bit SCLx  2011-2015 Microchip Technology Inc. DS40001609E-page 203...
  • Page 203 At completion of Start bit, SDAx = 1, SDAx = 1, hardware clears RSEN bit SCLx = 1 SCLx (no change) and sets SSPxIF 1st bit SDAx Write to SSPxBUF occurs here SCLx Repeated Start  2011-2015 Microchip Technology Inc. DS40001609E-page 204...
  • Page 204 (i.e., SSPxSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission.  2011-2015 Microchip Technology Inc. DS40001609E-page 205...
  • Page 205 PIC16(L)F1508/9 FIGURE 21-28: C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)  2011-2015 Microchip Technology Inc. DS40001609E-page 206...
  • Page 206 If the user writes the SSPxBUF when a receive is communication. already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).  2011-2015 Microchip Technology Inc. DS40001609E-page 207...
  • Page 207 PIC16(L)F1508/9 FIGURE 21-29: C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)  2011-2015 Microchip Technology Inc. DS40001609E-page 208...
  • Page 208 ACKEN = 1, ACKDT = 0 SDAx SCLx SSPxIF Cleared in SSPxIF set at software Cleared in the end of receive software SSPxIF set at the end of Acknowledge sequence Note: T = one Baud Rate Generator period.  2011-2015 Microchip Technology Inc. DS40001609E-page 209...
  • Page 209 Control of the I C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is idle and the S and P bits are cleared.  2011-2015 Microchip Technology Inc. DS40001609E-page 210...
  • Page 210 SCLx = 0 by another source by the master. Bus collision has occurred. SDAx released by master SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF  2011-2015 Microchip Technology Inc. DS40001609E-page 211...
  • Page 211 SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because BCLxIF SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared by software SSPxIF SSPxIF and BCLxIF are cleared by software  2011-2015 Microchip Technology Inc. DS40001609E-page 212...
  • Page 212 SCLx pulled low after BRG time-out Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 ‘0’ BCLxIF SSPxIF Interrupts cleared SDAx = 0, SCLx = 1, by software set SSPxIF  2011-2015 Microchip Technology Inc. DS40001609E-page 213...
  • Page 213 ‘0’ SSPxIF FIGURE 21-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) SDAx SCLx SCLx goes low before SDAx, BCLxIF set BCLxIF. Release SDAx and SCLx. Interrupt cleared by software RSEN ‘0’ SSPxIF  2011-2015 Microchip Technology Inc. DS40001609E-page 214...
  • Page 214 SDAx asserted low SCLx BCLxIF ‘0’ ‘0’ SSPxIF FIGURE 21-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) SDAx SCLx goes low before SDAx goes high, Assert SDAx set BCLxIF SCLx BCLxIF ‘0’ ‘0’ SSPxIF  2011-2015 Microchip Technology Inc. DS40001609E-page 215...
  • Page 215 MSK<7:0> SSP1STAT — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I C™ mode. Legend: Page provides register information. Unimplemented, read as ‘1’. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 216...
  • Page 216 4 MHz 1 MHz 100 kHz Refer to the I/O port electrical and timing specifications in Table 29-9 Figure 29-7 to ensure the system Note: is designed to support the I/O timing requirements.  2011-2015 Microchip Technology Inc. DS40001609E-page 217...
  • Page 217 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty  2011-2015 Microchip Technology Inc. DS40001609E-page 218...
  • Page 218 When enabled, the SDAx and SCLx pins must be configured as inputs. SSPxADD values of 0, 1 or 2 are not supported for I C mode. SSPxADD value of ‘0’ is not supported. Use SSPM = 0000 instead.  2011-2015 Microchip Technology Inc. DS40001609E-page 219...
  • Page 219 For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I C module is not in the Idle mode, this bit may not be Note 1: set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).  2011-2015 Microchip Technology Inc. DS40001609E-page 220...
  • Page 220 This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.  2011-2015 Microchip Technology Inc. DS40001609E-page 221...
  • Page 221 10-Bit Slave mode – Least Significant Address Byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.  2011-2015 Microchip Technology Inc. DS40001609E-page 222...
  • Page 222: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (Eusart)

    10/14/2013 Data bus TXIE Interrupt TXREG register TXIF TX/CK Pin Buffer and Control Transmit Shift Register (TSR) TX_out TXEN TRMT Baud Rate Generator ÷ n BRG16 TX9D Multiplier SYNC BRGH SPBRGH SPBRGL BRG16  2011-2015 Microchip Technology Inc. DS40001609E-page 223...
  • Page 223 Register 22-1, Register 22-2 Register 22-3, respectively. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output.  2011-2015 Microchip Technology Inc. DS40001609E-page 224...
  • Page 224 I/O function must be disabled by clearing the corresponding ANSEL bit. The TXIF Transmitter Interrupt flag is set Note: when the TXEN enable bit is set.  2011-2015 Microchip Technology Inc. DS40001609E-page 225...
  • Page 225 Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) Word 1 TRMT bit Word 2 (Transmit Shift Transmit Shift Reg. Transmit Shift Reg. Reg. Empty Flag) This timing diagram shows two consecutive transmissions. Note:  2011-2015 Microchip Technology Inc. DS40001609E-page 226...
  • Page 226 TXREG EUSART Transmit Data Register TXSTA CSRC TXEN SYNC SENDB BRGH TRMT TX9D Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission. Page provides register information.  2011-2015 Microchip Technology Inc. DS40001609E-page 227...
  • Page 227 • GIE, Global Interrupt Enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits.  2011-2015 Microchip Technology Inc. DS40001609E-page 228...
  • Page 228 Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG.  2011-2015 Microchip Technology Inc. DS40001609E-page 229...
  • Page 229 OERR bit CREN This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, Note: causing the OERR (overrun) bit to be set.  2011-2015 Microchip Technology Inc. DS40001609E-page 230...
  • Page 230 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 TXSTA CSRC TXEN SYNC SENDB BRGH TRMT TX9D Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception. Page provides register information.  2011-2015 Microchip Technology Inc. DS40001609E-page 231...
  • Page 231 Section22.4.1 “Auto-Baud compensate for changes in the INTOSC frequency. There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency.  2011-2015 Microchip Technology Inc. DS40001609E-page 232...
  • Page 232 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. SREN/CREN overrides TXEN in Sync mode. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 233...
  • Page 233 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware.  2011-2015 Microchip Technology Inc. DS40001609E-page 234...
  • Page 234 Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care  2011-2015 Microchip Technology Inc. DS40001609E-page 235...
  • Page 235 To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is idle before changing the system clock.  2011-2015 Microchip Technology Inc. DS40001609E-page 236...
  • Page 236 SPBRGH BRG<15:8> 236* TXSTA CSRC TXEN SYNC SENDB BRGH TRMT TX9D Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator. Page provides register information.  2011-2015 Microchip Technology Inc. DS40001609E-page 237...
  • Page 237 10378 -0.37 10417 0.00 10473 0.53 19.2k 19.23k 0.16 19.20k 0.00 19.23k 0.16 19.20k 0.00 57.6k 56.82k -1.36 57.60k 0.00 58.82k 2.12 57.60k 0.00 115.2k 113.64k -1.36 115.2k 0.00 111.1k -3.55 115.2k 0.00  2011-2015 Microchip Technology Inc. DS40001609E-page 238...
  • Page 238 19.2k 19.23k 0.16 19.23k 0.16 19.20k 0.00 — — — 57.6k 55556 -3.55 — — — 57.60k 0.00 — — — 115.2k — — — — — — 115.2k 0.00 — — —  2011-2015 Microchip Technology Inc. DS40001609E-page 239...
  • Page 239 10473 0.53 10417 0.00 19.2k 19.23k 0.16 19.23k 0.16 19.20k 0.00 19.23k 0.16 57.6k 57.14k -0.79 58.82k 2.12 57.60k 0.00 — — — 115.2k 117.6k 2.12 111.1k -3.55 115.2k 0.00 — — —  2011-2015 Microchip Technology Inc. DS40001609E-page 240...
  • Page 240 Stop bit BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRGL SPBRGH The ABD sequence requires the EUSART module to be configured in Asynchronous mode. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 241...
  • Page 241 RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character.  2011-2015 Microchip Technology Inc. DS40001609E-page 242...
  • Page 242 If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is Note 1: still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set.  2011-2015 Microchip Technology Inc. DS40001609E-page 243...
  • Page 243 TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit)  2011-2015 Microchip Technology Inc. DS40001609E-page 244...
  • Page 244 Clock polarity is selected with the SCKP bit of the BAUDCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock.  2011-2015 Microchip Technology Inc. DS40001609E-page 245...
  • Page 245 EUSART Transmit Data Register 225* TXSTA CSRC TXEN SYNC SENDB BRGH TRMT TX9D — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission. Legend: Page provides register information.  2011-2015 Microchip Technology Inc. DS40001609E-page 246...
  • Page 246 FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters  2011-2015 Microchip Technology Inc. DS40001609E-page 247...
  • Page 247 TRISB3 TRISB2 TRISB1 TRISB0 TXSTA CSRC TXEN SYNC SENDB BRGH TRMT TX9D Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception. Page provides register information.  2011-2015 Microchip Technology Inc. DS40001609E-page 248...
  • Page 248 EUSART Transmit Data Register 225* TXSTA CSRC TXEN SYNC SENDB BRGH TRMT TX9D Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Page provides register information.  2011-2015 Microchip Technology Inc. DS40001609E-page 249...
  • Page 249 TRISB3 TRISB2 TRISB1 TRISB0 TXSTA CSRC TXEN SYNC SENDB BRGH TRMT TX9D Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception. Page provides register information.  2011-2015 Microchip Technology Inc. DS40001609E-page 250...
  • Page 250: Pulse-Width Modulation (Pwm) Module

    Comparator PWMx TMR2 Module TRIS Control PWMxPOL TMR2 Comparator T2_match Note 1: 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to create 10-bit time-base.  2011-2015 Microchip Technology Inc. DS40001609E-page 251...
  • Page 251   4 T    PWM Period FIGURE 23-2: PWM OUTPUT (TMR2 Prescale Value) Rev. 10-000023A 7/30/2013 = 1/F Note: Pulse Width TMR2 = 0 TMR2 = PWMxDC TMR2 = PR2  2011-2015 Microchip Technology Inc. DS40001609E-page 252...
  • Page 252 Refer to Section 5.0 “Oscillator Module (With for additional details. Fail-Safe Clock Monitor)” 23.1.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the PWM registers to their Reset states.  2011-2015 Microchip Technology Inc. DS40001609E-page 253...
  • Page 253 If it is not critical to start with a complete PWM signal, then move Step 8 to replace Step 4. 2: For operation with other peripherals only, disable PWMx pin outputs.  2011-2015 Microchip Technology Inc. DS40001609E-page 254...
  • Page 254 5 PWMxOUT: PWM Module Output Value bit bit 4 PWMxPOL: PWMx Output Polarity Select bit 1 = PWM output is active-low 0 = PWM output is active-high bit 3-0 Unimplemented: Read as ‘0’  2011-2015 Microchip Technology Inc. DS40001609E-page 255...
  • Page 255 TRISC1 TRISC0 - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM. Legend: Page provides register information. Unimplemented, read as ‘1’. Note  2011-2015 Microchip Technology Inc. DS40001609E-page 256...
  • Page 256: Configurable Logic Cell (Clc)

    LCx_out LCx_in[7] lcxq Function CLCx lcxg3 LCx_in[8] LCx_in[9] lcxg4 LCx_in[10] LCxPOL LCx_in[11] LCx_in[12] LCxMODE<2:0> Interrupt LCx_in[13] LCx_in[14] LCx_in[15] LCXINTP set bit LCXINTN CLCxIF Interrupt Note 1: See Figure 24-2. 2: See Figure 24-3.  2011-2015 Microchip Technology Inc. DS40001609E-page 257...
  • Page 257 LC4_out LC4_out LC4_out LCx_in[12] — — NCO1_out LFINTOSC TX_out SCK_out (MSSP) (EUSART) LCx_in[13] — — HFINTOSC LFINTOSC SDO_out (MSSP) LCx_in[14] — — PWM3_out PWM1_out PWM2_out PWM1_out LCx_in[15] — — PWM4_out PWM2_out PWM3_out PWM4_out  2011-2015 Microchip Technology Inc. DS40001609E-page 258...
  • Page 258 • Gate 3: CLCxGLS2 (Register 24-7) • Gate 4: CLCxGLS3 (Register 24-8) Register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register.  2011-2015 Microchip Technology Inc. DS40001609E-page 259...
  • Page 259 CLC is enabled, the CPU will go idle during Sleep, but the CLC will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current.  2011-2015 Microchip Technology Inc. DS40001609E-page 260...
  • Page 260 Data GATE 3 LCx_in[31] 11111 lcxg3 LCxD3S<4:0> (Same as Data GATE 1) Data GATE 4 LCx_in[0] 00000 lcxg4 (Same as Data GATE 1) lcxd4T lcxd4N LCx_in[31] 11111 LCxD4S<4:0> All controls are undefined at power-up. Note:  2011-2015 Microchip Technology Inc. DS40001609E-page 261...
  • Page 261 LCxMODE<2:0> = 100 LCxMODE<2:0> = 101 J-K Flip-Flop with R 1-Input Transparent Latch with S and R lcxg4 lcxg2 lcxq lcxg2 lcxq lcxg1 lcxg4 lcxg3 lcxg3 lcxg1 LCxMODE<2:0> = 110 LCxMODE<2:0> = 111  2011-2015 Microchip Technology Inc. DS40001609E-page 262...
  • Page 262 100 = Cell is 1-input D flip-flop with S and R 011 = Cell is S-R latch 010 = Cell is 4-input AND 001 = Cell is OR-XOR 000 = Cell is AND-OR  2011-2015 Microchip Technology Inc. DS40001609E-page 263...
  • Page 263 0 LCxG1POL: Gate 1 Output Polarity Control bit 1 = The output of gate 1 is inverted when applied to the logic cell 0 = The output of gate 1 is not inverted  2011-2015 Microchip Technology Inc. DS40001609E-page 264...
  • Page 264 011 = LCx_in[3] is selected for lcxd1 010 = LCx_in[2] is selected for lcxd1 001 = LCx_in[1] is selected for lcxd1 000 = LCx_in[0] is selected for lcxd1 Table 24-1 for signal names associated with inputs. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 265...
  • Page 265 011 = LCx_in[11] is selected for lcxd3 010 = LCx_in[10] is selected for lcxd3 001 = LCx_in[9] is selected for lcxd3 000 = LCx_in[8] is selected for lcxd3 Table 24-1 for signal names associated with inputs. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 266...
  • Page 266 0 = lcxd1T is not gated into lcxg1 bit 0 LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg1 0 = lcxd1N is not gated into lcxg1  2011-2015 Microchip Technology Inc. DS40001609E-page 267...
  • Page 267 0 = lcxd1T is not gated into lcxg2 bit 0 LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg2 0 = lcxd1N is not gated into lcxg2  2011-2015 Microchip Technology Inc. DS40001609E-page 268...
  • Page 268 0 = lcxd1T is not gated into lcxg3 bit 0 LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg3 0 = lcxd1N is not gated into lcxg3  2011-2015 Microchip Technology Inc. DS40001609E-page 269...
  • Page 269 0 = lcxd1T is not gated into lcxg4 bit 0 LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg4 0 = lcxd1N is not gated into lcxg4  2011-2015 Microchip Technology Inc. DS40001609E-page 270...
  • Page 270 Unimplemented: Read as ‘0’ bit 3 MLC4OUT: Mirror copy of LC4OUT bit bit 2 MLC3OUT: Mirror copy of LC3OUT bit bit 1 MLC2OUT: Mirror copy of LC2OUT bit bit 0 MLC1OUT: Mirror copy of LC1OUT bit  2011-2015 Microchip Technology Inc. DS40001609E-page 271...
  • Page 271 — — — TRISB TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISC — = unimplemented read as ‘0’,. Shaded cells are not used for CLC module. Legend: Unimplemented, read as ‘1’. Note  2011-2015 Microchip Technology Inc. DS40001609E-page 272...
  • Page 272: Numerically Controlled Oscillator (Nco) Module

    • CLKIN pin The NCOx clock source is selected by configuring the NxCKS<2:0> bits in the NCOxCLK register. EQUATION 25-1:  NCO Clock Frequency Increment Value --------------------------------------------------------------------------------------------------------------- - OVERFLOW n = Accumulator width in bits  2011-2015 Microchip Technology Inc. DS40001609E-page 273...
  • Page 273 FIGURE 25-1: NUMERICALLY CONTROLLED OSCILLATOR (NCOx) MODULE SIMPLIFIED BLOCK DIAGRAM NCOxINCH NCOxINCL Rev. 10-000028A 7/30/2013 INCBUFH INCBUFL NCO_overflow Adder HFINTOSC NCOx_clk NCOxACCU NCOxACCH NCOxACCL LCx_out NCO1CLK NCO_interrupt set bit NxCKS<1:0> NCOxIF Fixed Duty Cycle Mode Circuitry NxOE TRIS bit NCOx NxPFM NxPOL NCOx_out...
  • Page 274 Section 11.1 “Alternate Pin Function” code or other peripherals. Accomplish this by reading more information. the NxOUT (read-only) bit of the NCOxCON register. The NCOx output signal is available to the following peripherals: • CLC • CWG  2011-2015 Microchip Technology Inc. DS40001609E-page 275...
  • Page 275 FIGURE 25-2: NCO – FIXED DUTY CYCLE (FDC) AND PULSE FREQUENCY MODE (PFM) OUTPUT OPERATION DIAGRAM Rev. 10-000029A 11/7/2013 NCOx Clock Source NCOx Increment 4000h 4000h 4000h Value NCOx Accumulator 00000h 04000h 08000h FC000h 00000h 04000h 08000h FC000h 00000h 04000h 08000h Value NCO_overflow NCO_interrupt...
  • Page 276 10 = LC1_out 01 = F 00 = HFINTOSC (16 MHz) Note 1: NxPWS applies only when operating in Pulse Frequency mode. If NCOx pulse width is greater than NCO_overflow period, operation is indeterminate.  2011-2015 Microchip Technology Inc. DS40001609E-page 277...
  • Page 277 -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 ACC<19:16>: NCO Accumulator, Upper Byte  2011-2015 Microchip Technology Inc. DS40001609E-page 278...
  • Page 278 TRISC0 x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for NCOx Legend: module. Unimplemented, read as ‘1’. Note  2011-2015 Microchip Technology Inc. DS40001609E-page 279...
  • Page 279: Complementary Waveform Generator (Cwg) Module

    The clock sources are selected using the G1CS0 bit of active-low. However, polarity does not affect the the CWGxCON0 register (Register 26-1). override levels. Output polarity is selected with the GxPOLA and GxPOLB bits of the CWGxCON0 register.  2011-2015 Microchip Technology Inc. DS40001609E-page 280...
  • Page 280 FIGURE 26-1: SIMPLIFIED CWG BLOCK DIAGRAM Rev. 10-000123A 7/9/2015 GxASDLA GxASDLA = 01 ‘0' GxCS ‘1' CWGxDBR cwg_clock HFINTOSC CWGxA GxIS TRISx GxOEA C1OUT_async GxPOLA Input Source C2OUT_async CWGxDBF PWM1_out PWM2_out PWM3_out PWM4_out NCO1_out GxOEB LC1_out TRISx GxPOLB CWGxB CWG1FLT (INT pin) GxASDSFLT C1OUT_async GxASDSC1...
  • Page 281 A count of 0 (zero), indicates that no dead band is present. If the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output.  2011-2015 Microchip Technology Inc. DS40001609E-page 282...
  • Page 282 FIGURE 26-3: DEAD-BAND OPERATION, CWGxDBR = 01H, CWGxDBF = 02H cwg_clock Input Source CWGxA CWGxB FIGURE 26-4: DEAD-BAND OPERATION, CWGxDBR = 03H, CWGxDBF = 04H, SOURCE SHORTER THAN DEAD BAND cwg_clock Input Source CWGxA CWGxB source shorter than dead band...
  • Page 283 Shutdown inputs are selected in the CWGxCON2 register. (Register 26-3). Shutdown inputs are level sensitive, not Note: edge sensitive. The shutdown state can- not be cleared, except by disabling auto- shutdown, as long as the shutdown input level persists.  2011-2015 Microchip Technology Inc. DS40001609E-page 284...
  • Page 284 CWGxA and CWGxB to be used to configure those pins as outputs. If auto-restart is to be used, set the GxARSEN bit and the GxASE bit will be cleared automati- cally. Otherwise, clear the GxASE bit to start the CWG.  2011-2015 Microchip Technology Inc. DS40001609E-page 285...
  • Page 285 FIGURE 26-5: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (GxARSEN = 0,GxASDLA = 01, GxASDLB = 01) GxASE Cleared by Software Shutdown Event Ceases CWG Input Source Shutdown Source GxASE CWG1A Tri-State (No Pulse) CWG1B Tri-State (No Pulse) No Shutdown Output Resumes Shutdown FIGURE 26-6: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (GxARSEN = 1,GxASDLA = 01, GxASDLB = 01) Shutdown Event Ceases...
  • Page 286 GxPOLA: CWGxA Output Polarity bit 1 = Output is inverted polarity 0 = Output is normal polarity bit 2-1 Unimplemented: Read as ‘0’ bit 0 GxCS0: CWGx Clock Source Select bit 1 = HFINTOSC 0 = F  2011-2015 Microchip Technology Inc. DS40001609E-page 287...
  • Page 287 110 = NCO1 – NCO1_out 101 = PWM4 – PWM4_out 100 = PWM3 – PWM3_out 011 = PWM2 – PWM2_out 010 = PWM1 – PWM1_out 001 = Comparator C2– C2OUT_async 000 = Comparator C1 – C1OUT_async  2011-2015 Microchip Technology Inc. DS40001609E-page 288...
  • Page 288 0 = CWG1FLT input has no effect on shutdown bit 0 GxASDSCLC2: CWG Auto-shutdown on CLC2 Enable bit 1 = Shutdown when CLC2 output (LC2_out) is high 0 = CLC2 output has no effect on shutdown  2011-2015 Microchip Technology Inc. DS40001609E-page 289...
  • Page 289 11 1110 = 62-63 counts of dead band    00 0010 = 2-3 counts of dead band 00 0001 = 1-2 counts of dead band 00 0000 = 0 counts of dead band. Dead-band generation is bypassed.  2011-2015 Microchip Technology Inc. DS40001609E-page 290...
  • Page 290 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by CWG. Legend: Unimplemented, read as ‘1’. Note  2011-2015 Microchip Technology Inc. DS40001609E-page 291...
  • Page 291: In-Circuit Serial Programming™ (Icsp™)

    If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See for more Section 6.5 “MCLR” information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode.  2011-2015 Microchip Technology Inc. DS40001609E-page 292...
  • Page 292 FIGURE 27-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING Rev. 10-000129A 7/30/2013 External Device to be Programming Programmed Signals MCLR/V Data ICSPDAT Clock ICSPCLK To Normal Connections * Isolation devices (as required).  2011-2015 Microchip Technology Inc. DS40001609E-page 293...
  • Page 293: Instruction Set Summary

    All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a TABLE 28-2: ABBREVIATION hexadecimal digit. DESCRIPTIONS Field Description Program Counter Time-Out bit Carry bit Digit Carry bit Zero bit Power-Down bit  2011-2015 Microchip Technology Inc. DS40001609E-page 294...
  • Page 294 FSR Offset instructions OPCODE k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions OPCODE n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only OPCODE  2011-2015 Microchip Technology Inc. DS40001609E-page 295...
  • Page 295 Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle.  2011-2015 Microchip Technology Inc. DS40001609E-page 296...
  • Page 296 If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. See Table in the MOVIW and MOVWI instruction descriptions.  2011-2015 Microchip Technology Inc. DS40001609E-page 297...
  • Page 297 Add W, the Carry flag and data mem- ory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.  2011-2015 Microchip Technology Inc. DS40001609E-page 298...
  • Page 298 Bit Set f Syntax: [ label ] BSF 0  f  127 Operands: 0  b  7 1  (f<b>) Operation: Status Affected: None Description: Bit ‘b’ in register ‘f’ is set.  2011-2015 Microchip Technology Inc. DS40001609E-page 299...
  • Page 299 ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None 00h  (W) Operation: 1  Z Status Affected: Description: W register is cleared. Zero bit (Z) is set.  2011-2015 Microchip Technology Inc. DS40001609E-page 300...
  • Page 300 ‘f’. If ‘d’ is ‘0’, the result is placed in in the W register. If ‘d’ is ‘1’, the result the W register. If ‘d’ is ‘1’, the result is is placed back in register ‘f’. placed back in register ‘f’.  2011-2015 Microchip Technology Inc. DS40001609E-page 301...
  • Page 301 Carry flag. A ‘0’ is shifted into the MSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. register f  2011-2015 Microchip Technology Inc. DS40001609E-page 302...
  • Page 302 Move literal to BSR Syntax: [ label ] MOVLB k 0  k  31 Operands: k  BSR Operation: Status Affected: None Description: The 5-bit literal ‘k’ is loaded into the Bank Select Register (BSR).  2011-2015 Microchip Technology Inc. DS40001609E-page 303...
  • Page 303 FSRn. FSRn is limited to the range 0000h - FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. The increment/decrement operation on FSRn WILL NOT affect any Status bits.  2011-2015 Microchip Technology Inc. DS40001609E-page 304...
  • Page 304 1110 0110 RETLW k1 ;Begin table RETLW k2 ; After Instruction • REG1 1110 0110 • 1100 1100 • RETLW kn ; End of table Before Instruction 0x07 After Instruction value of k8  2011-2015 Microchip Technology Inc. DS40001609E-page 305...
  • Page 305 Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s comple- ment method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.  2011-2015 Microchip Technology Inc. DS40001609E-page 306...
  • Page 306 W register. If ‘d’ When ‘f’ = 6, TRISB is loaded. is ‘1’, the result is stored back in regis- When ‘f’ = 7, TRISC is loaded. ter ‘f’.  2011-2015 Microchip Technology Inc. DS40001609E-page 307...
  • Page 307 PIC16(L)F1508/9 NOTES:  2011-2015 Microchip Technology Inc. DS40001609E-page 308...
  • Page 308: Electrical Specifications

    This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.  2011-2015 Microchip Technology Inc. DS40001609E-page 309...
  • Page 309 (16 MHz < Fosc  20 MHz) ..................+2.5V DDMIN ............................ +5.5V DDMAX — Operating Ambient Temperature Range Industrial Temperature ............................-40°C ............................ +85°C Extended Temperature ............................-40°C ..........................+125°C See Parameter D001, DC Characteristics: Supply Voltage. Note 1:  2011-2015 Microchip Technology Inc. DS40001609E-page 310...
  • Page 310 +125°C, PIC16LF1508/9 ONLY FIGURE 29-2: Rev. 10-000131A 8/5/2013 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 29-8 for each Oscillator mode’s supported frequencies.  2011-2015 Microchip Technology Inc. DS40001609E-page 311...
  • Page 311 Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which V can be lowered in Sleep mode without losing RAM data. Note 1: Figure 29-3, POR and POR REARM with Slow Rising V  2011-2015 Microchip Technology Inc. DS40001609E-page 312...
  • Page 312 POR AND POR REARM WITH SLOW RISING V PORR NPOR POR REARM VLOW (3) When NPOR is low, the device is held in Reset. Note 1: 1 s typical. 2.7 s typical. VLOW  2011-2015 Microchip Technology Inc. DS40001609E-page 313...
  • Page 313 For RC oscillator configurations, current through R is not included. The current through the resistor can be extended by the formula IR = V (mA) with R in k.  2011-2015 Microchip Technology Inc. DS40001609E-page 314...
  • Page 314 For RC oscillator configurations, current through R is not included. The current through the resistor can be extended by the formula IR = V (mA) with R in k.  2011-2015 Microchip Technology Inc. DS40001609E-page 315...
  • Page 315 For RC oscillator configurations, current through R is not included. The current through the resistor can be extended by the formula IR = V (mA) with R in k.  2011-2015 Microchip Technology Inc. DS40001609E-page 316...
  • Page 316 The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V ADC clock source is FRC.  2011-2015 Microchip Technology Inc. DS40001609E-page 317...
  • Page 317 The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V ADC clock source is FRC.  2011-2015 Microchip Technology Inc. DS40001609E-page 318...
  • Page 318 Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.  2011-2015 Microchip Technology Inc. DS40001609E-page 319...
  • Page 319 Derated Power — = PD )/ Note 1: I is current to run the chip alone without driving any load on the output pins. 2: T = Ambient Temperature; T = Junction Temperature  2011-2015 Microchip Technology Inc. DS40001609E-page 320...
  • Page 320 T0CKI I/O PORT T1CKI MCLR Uppercase letters and their meanings: Fall Period High Rise Invalid (High-impedance) Valid High-impedance FIGURE 29-4: LOAD CONDITIONS Rev. 10-000133A 8/1/2013 Load Condition Legend: CL=50 pF for all pins  2011-2015 Microchip Technology Inc. DS40001609E-page 321...
  • Page 321 All devices are tested to operate at “min” values with an external clock applied to CLKIN pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.  2011-2015 Microchip Technology Inc. DS40001609E-page 322...
  • Page 322 AND TEMPERATURE Rev. 10-000135A 7/30/2013 ±12% -4.5% to +7% ±4.5% ±12% Figure 30-72: “HFINTOSC Accuracy Over Temperature, V = 1.8V, PIC16LF1508/9 Only”, and Note: 30-73: “HFINTOSC Accuracy Over Temperature, 2.3V V  5.5V”. Figure  2011-2015 Microchip Technology Inc. DS40001609E-page 323...
  • Page 323 These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in EXTRC mode where CLKOUT output is 4 x T  2011-2015 Microchip Technology Inc. DS40001609E-page 324...
  • Page 324 PIC16(L)F1508/9 FIGURE 29-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING MCLR Internal PWRT Time-out Start-up Time Internal Reset Watchdog Timer Reset I/O pins Note 1:Asserted low.  2011-2015 Microchip Technology Inc. DS40001609E-page 325...
  • Page 325 0.1 F and 0.01 F values in parallel are recommended. FIGURE 29-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS and V HYST (Device in Brown-out Reset) (Device not in Brown-out Reset) Reset (due to BOR)  2011-2015 Microchip Technology Inc. DS40001609E-page 326...
  • Page 326 Timers in Sync Increment mode These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2011-2015 Microchip Technology Inc. DS40001609E-page 327...
  • Page 327 † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Table 29-9 for OS18 and OS19 rise and fall times. Note 1:See  2011-2015 Microchip Technology Inc. DS40001609E-page 328...
  • Page 328 2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. 3: See for operating characterization. Section 30.0 “DC and AC Characteristics Graphs and Charts” 4: ADC V is selected by ADPREF<0> bit.  2011-2015 Microchip Technology Inc. DS40001609E-page 329...
  • Page 329 Sampling Stopped AD132 Sample Note 1:If the ADC clock source is selected as FRC, a time of T is added before the ADC clock starts. This allows the SLEEP instruction to be executed.  2011-2015 Microchip Technology Inc. DS40001609E-page 330...
  • Page 330 These parameters are characterized but not tested. for operating characterization. Note 1: Section 30.0 “DC and AC Characteristics Graphs and Charts” Response time measured with one comparator input at V /2, while the other input transitions from V  2011-2015 Microchip Technology Inc. DS40001609E-page 331...
  • Page 331  5.5V US122 Data-out rise time and fall time — DTRF 1.8V  V  5.5V — FIGURE 29-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING US125 US126 Note: Refer to Figure 29-4 for load conditions.  2011-2015 Microchip Technology Inc. DS40001609E-page 332...
  • Page 332 (unless otherwise stated) Param. Symbol Characteristic Min. Max. Units Conditions US125 T SYNC RCV (Master and Slave) Data-hold before CK  (DT hold time) — Data-hold after CK  (DT hold time) US126 T —  2011-2015 Microchip Technology Inc. DS40001609E-page 333...
  • Page 333 (CKP = 1) SP80 SP78 bit 6 - - - - - -1 SP75, SP76 MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 29-4 for load conditions.  2011-2015 Microchip Technology Inc. DS40001609E-page 334...
  • Page 334 (CKP = 1) SP80 bit 6 - - - - - -1 SP77 SP75, SP76 MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 29-4 for load conditions.  2011-2015 Microchip Technology Inc. DS40001609E-page 335...
  • Page 335 + 40 — — These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2011-2015 Microchip Technology Inc. DS40001609E-page 336...
  • Page 336 These parameters are characterized but not tested. FIGURE 29-21: C BUS DATA TIMING SP100 SP102 SP103 SP101 SP90 SP106 SP107 SP92 SP91 SP110 SP109 SP109 Note: Refer to Figure 29-4 for load conditions.  2011-2015 Microchip Technology Inc. DS40001609E-page 337...
  • Page 337 SDA line T max. + T = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification), before the SCL line is released.  2011-2015 Microchip Technology Inc. DS40001609E-page 338...
  • Page 338: Dc And Ac Characteristics Graphs And Charts

    Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.” “ represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each temperature range.  2011-2015 Microchip Technology Inc. DS40001609E-page 339...
  • Page 339 , LP OSCILLATOR, F = 32 kHz, PIC16LF1508/9 ONLY Max: 85°C + 3 Max. Typical: 25°C Typical FIGURE 30-2: , LP OSCILLATOR, F = 32 kHz, PIC16F1508/9 ONLY Max. Max: 85°C + 3 Typical: 25°C Typical  2011-2015 Microchip Technology Inc. DS40001609E-page 340...
  • Page 340 4 MHz XT 1 MHz XT 1 MHz EXTRC FIGURE 30-4: MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16LF1508/9 ONLY Max: 85°C + 3 4 MHz XT 4 MHz EXTRC 1 MHz XT 1 MHz EXTRC  2011-2015 Microchip Technology Inc. DS40001609E-page 341...
  • Page 341 4 MHz XT 1 MHz XT 1 MHz EXTRC FIGURE 30-6: MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16F1508/9 ONLY Max: 85°C + 3 4 MHz XT 4 MHz EXTRC 1 MHz XT 1 MHz EXTRC  2011-2015 Microchip Technology Inc. DS40001609E-page 342...
  • Page 342 = 32 kHz, PIC16LF1508/9 ONLY Max. Typical Max: 85°C + 3 Typical: 25°C FIGURE 30-8: , EXTERNAL CLOCK (ECL), LOW-POWER MODE, F = 32 kHz, PIC16F1508/9 ONLY Max. Typical Max: 85°C + 3 Typical: 25°C  2011-2015 Microchip Technology Inc. DS40001609E-page 343...
  • Page 343 = 500 kHz, PIC16LF1508/9 ONLY Max: 85°C + 3 Typical: 25°C Max. Typical FIGURE 30-10: , EXTERNAL CLOCK (ECL), LOW-POWER MODE, F = 500 kHz, PIC16F1508/9 ONLY Max. Typical Max: 85°C + 3 Typical: 25°C  2011-2015 Microchip Technology Inc. DS40001609E-page 344...
  • Page 344 TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM POWER MODE, PIC16LF1508/9 ONLY Typical: 25°C 4 MHz 1 MHz FIGURE 30-12: MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM POWER MODE, PIC16LF1508/9 ONLY Max: 85°C + 3 4 MHz 1 MHz  2011-2015 Microchip Technology Inc. DS40001609E-page 345...
  • Page 345 TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM POWER MODE, PIC16F1508/9 ONLY 4 MHz Typical: 25°C 1 MHz FIGURE 30-14: MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM POWER MODE, PIC16F1508/9 ONLY 4 MHz Max: 85°C + 3 1 MHz  2011-2015 Microchip Technology Inc. DS40001609E-page 346...
  • Page 346 TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16LF1508/9 ONLY 20 MHz Typical: 25°C 16 MHz 8 MHz FIGURE 30-16: MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16LF1508/9 ONLY 20 MHz Max: 85°C + 3 16 MHz 8 MHz  2011-2015 Microchip Technology Inc. DS40001609E-page 347...
  • Page 347 TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16F1508/9 ONLY 20 MHz Typical: 25°C 16 MHz 8 MHz FIGURE 30-18: MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC16F1508/9 ONLY 20 MHz Max: 85°C + 3 16 MHz 8 MHz  2011-2015 Microchip Technology Inc. DS40001609E-page 348...
  • Page 348 , LFINTOSC, F = 31 kHz, PIC16LF1508/9 ONLY Max. Max: 85°C + 3 Typical: 25°C Typical FIGURE 30-20: , LFINTOSC, F = 31 kHz, PIC16F1508/9 ONLY Max. Typical Max: 85°C + 3 Typical: 25°C  2011-2015 Microchip Technology Inc. DS40001609E-page 349...
  • Page 349 , MFINTOSC, F = 500 kHz, PIC16LF1508/9 ONLY Max: 85°C + 3 Typical: 25°C Max. Typical FIGURE 30-22: , MFINTOSC, F = 500 kHz, PIC16F1508/9 ONLY Max: 85°C + 3 Max. Typical: 25°C Typical  2011-2015 Microchip Technology Inc. DS40001609E-page 350...
  • Page 350 PIC16(L)F1508/9 FIGURE 30-23: TYPICAL, HFINTOSC, PIC16LF1508/9 ONLY Typical: 25°C 16 MHz 8 MHz 4 MHz FIGURE 30-24: MAXIMUM, HFINTOSC, PIC16LF1508/9 ONLY Max: 85°C + 3 16 MHz 8 MHz 4 MHz  2011-2015 Microchip Technology Inc. DS40001609E-page 351...
  • Page 351 PIC16(L)F1508/9 FIGURE 30-25: TYPICAL, HFINTOSC, PIC16F1508/9 ONLY 16 MHz 8 MHz 4 MHz Typical: 25°C FIGURE 30-26: MAXIMUM, HFINTOSC, PIC16F1508/9 ONLY 16 MHz 8 MHz 4 MHz Max: 85°C + 3  2011-2015 Microchip Technology Inc. DS40001609E-page 352...
  • Page 352 PIC16(L)F1508/9 FIGURE 30-27: TYPICAL, HS OSCILLATOR, PIC16LF1508/9 ONLY Typical: 25°C 20 MHz 8 MHz 4 MHz FIGURE 30-28: MAXIMUM, HS OSCILLATOR, PIC16LF1508/9 ONLY Max: 85°C + 3 20 MHz 8 MHz 4 MHz  2011-2015 Microchip Technology Inc. DS40001609E-page 353...
  • Page 353 PIC16(L)F1508/9 FIGURE 30-29: TYPICAL, HS OSCILLATOR, PIC16F1508/9 ONLY 20 MHz Typical: 25°C 8 MHz 4 MHz FIGURE 30-30: MAXIMUM, HS OSCILLATOR, PIC16F1508/9 ONLY Max: 85°C + 3 20 MHz 8 MHz 4 MHz  2011-2015 Microchip Technology Inc. DS40001609E-page 354...
  • Page 354 BASE, LOW-POWER SLEEP MODE, PIC16LF1508/9 ONLY Max: 85°C + 3 85°C Typical: 25°C Max. Typical FIGURE 30-32: BASE, LOW-POWER SLEEP MODE, VREGPM = 1, PIC16F1508/9 ONLY Max. Max. Max: 85°C + 3 Typical: 25°C Typical  2011-2015 Microchip Technology Inc. DS40001609E-page 355...
  • Page 355 FIGURE 30-33: , WATCHDOG TIMER (WDT), PIC16LF1508/9 ONLY Max: 85°C + 3 Typical: 25°C Max. Typical FIGURE 30-34: , WATCHDOG TIMER (WDT), PIC16F1508/9 ONLY Max. Typical Typical Max: 85°C + 3 Typical: 25°C  2011-2015 Microchip Technology Inc. DS40001609E-page 356...
  • Page 356 , FIXED VOLTAGE REFERENCE (FVR), PIC16LF1508/9 ONLY Max: 85°C + 3 Max: 85°C + 3 Typical: 25°C Max. Typical FIGURE 30-36: , FIXED VOLTAGE REFERENCE (FVR), PIC16F1508/9 ONLY Max. Typical Max: 85°C + 3 Typical: 25°C  2011-2015 Microchip Technology Inc. DS40001609E-page 357...
  • Page 357 , BROWN-OUT RESET (BOR), BORV = 0, PIC16LF1508/9 ONLY Max. Max. Max: 85°C + 3 Typical: 25°C Typical FIGURE 30-38: , BROWN-OUT RESET (BOR), BORV = 1, PIC16LF1508/9 ONLY Max. Max: 85°C + 3 Typical: 25°C Typical Typical  2011-2015 Microchip Technology Inc. DS40001609E-page 358...
  • Page 358 , BROWN-OUT RESET (BOR), BORV = 0, PIC16F1508/9 ONLY Max. Max: 85°C + 3 Typical: 25°C Typical FIGURE 30-40: , BROWN-OUT RESET (BOR), BORV = 1, PIC16F1508/9 ONLY Max. Max: 85°C + 3 Typical: 25°C Typical  2011-2015 Microchip Technology Inc. DS40001609E-page 359...
  • Page 359 Max: 85°C + 3 Max: 85°C + 3 Typical: 25°C Max. Typical FIGURE 30-42: , SECONDARY OSCILLATOR, F = 32 kHz, PIC16F1508/9 ONLY Max: 85°C + 3 Max: 85°C + 3 Typical: 25°C Max. Typical Typical  2011-2015 Microchip Technology Inc. DS40001609E-page 360...
  • Page 360 , COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC16LF1508/9 ONLY Max. Typical Typical Max: 85°C + 3 Typical: 25°C FIGURE 30-44: , COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC16F1508/9 ONLY Max. Typical Max: 85°C + 3 Typical: 25°C  2011-2015 Microchip Technology Inc. DS40001609E-page 361...
  • Page 361 Max. Typical Typical Max: 85°C + 3 Typical: 25°C Typical: 25 C FIGURE 30-46: , COMPARATOR, NORMAL POWER MODE (CxSP = 1), PIC16F1508/9 ONLY Max. Typical Typical Max: 85°C + 3 Typical: 25°C  2011-2015 Microchip Technology Inc. DS40001609E-page 362...
  • Page 362 Typical (25°C) Max. (125°C) (mA) FIGURE 30-48: vs. I OVER TEMPERATURE, V = 5.5V, PIC16F1508/9 ONLY Max: 125°C + 3 Max. (125°C) Typical: 25°C Min: -40°C - 3 Typical (25°C) Min. (-40°C) (mA)  2011-2015 Microchip Technology Inc. DS40001609E-page 363...
  • Page 363 Min. (-40°C) Typical (25°C) Max. (125°C) (mA) FIGURE 30-50: vs. I OVER TEMPERATURE, V = 3.0V Max: 125°C + 3 Typical: 25°C Min: -40°C - 3 Min. (-40°C) Typical (25°C) Max. (125°C) (mA)  2011-2015 Microchip Technology Inc. DS40001609E-page 364...
  • Page 364 -2.0 -1.5 -1.0 -0.5 (mA) FIGURE 30-52: vs. I OVER TEMPERATURE, V = 1.8V, PIC16LF1508/9 ONLY Max: 125°C + 3 Typical: 25°C Min: -40°C - 3 Max. (125°C) Typical (25°C) Min. (-40°C) (mA)  2011-2015 Microchip Technology Inc. DS40001609E-page 365...
  • Page 365 FIGURE 30-54: POR REARM VOLTAGE, PIC16F1508/9 ONLY 1.54 Max: Typical + 3 1.52 Typical: 25°C Min: Typical - 3 1.50 Max. 1.48 1.46 1.44 Typical 1.42 1.40 Min. 1.38 1.36 1.34 Temperature (°C)  2011-2015 Microchip Technology Inc. DS40001609E-page 366...
  • Page 366 Max: Typical + 3 Min: Typical - 3 1.80 Temperature (°C) FIGURE 30-56: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16LF1508/9 ONLY Max. Max: Typical + 3 Typical: 25°C Min: Typical - 3 Typical Min. Temperature (°C)  2011-2015 Microchip Technology Inc. DS40001609E-page 367...
  • Page 367 2.35 Min: Typical - 3 2.30 Temperature (°C) FIGURE 30-58: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16F1508/9 ONLY Max. Max: Typical + 3 Typical: 25°C Min: Typical - 3 Typical Min. Temperature (°C)  2011-2015 Microchip Technology Inc. DS40001609E-page 368...
  • Page 368 PIC16(L)F1508/9 FIGURE 30-59: BROWN-OUT RESET VOLTAGE, BORV = 0 2.80 2.75 Max. 2.70 Typical 2.65 Min. Max: Typical + 3 2.60 Min: Typical - 3 2.55 Temperature (°C)  2011-2015 Microchip Technology Inc. DS40001609E-page 369...
  • Page 369 Typical 2.20 2.10 2.00 Min. 1.90 1.80 Temperature (°C) FIGURE 30-61: LOW-POWER BROWN-OUT RESET HYSTERESIS, LPBOR = 0 Max: Typical + 3 Max. Typical: 25°C Min: Typical - 3 Typical Min. Temperature (°C)  2011-2015 Microchip Technology Inc. DS40001609E-page 370...
  • Page 370 Min: Typical - 3 (-40°C to +125°C) FIGURE 30-63: PWRT PERIOD Max: Typical + 3 (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3 (-40°C to +125°C) Max. Typical Min.  2011-2015 Microchip Technology Inc. DS40001609E-page 371...
  • Page 371 1) coming out of RESET or exiting Sleep mode for PIC12/16LFxxxx devices. 2) when exiting sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices In all other cases, the FVR is stable when released from RESET.  2011-2015 Microchip Technology Inc. DS40001609E-page 372...
  • Page 372 Max: Typical + 3 Typical: 25°C Min: Typical - 3 FIGURE 30-66: COMPARATOR HYSTERESIS, LOW-POWER MODE (CxSP = 0, CxHYS = 1) Max. Typical Max: Typical + 3 Min. Typical: 25°C Min: Typical - 3  2011-2015 Microchip Technology Inc. DS40001609E-page 373...
  • Page 373 Max: Typical + 3 Typical: 25°C FIGURE 30-68: COMPARATOR RESPONSE TIME OVER TEMPERATURE, NORMAL POWER MODE (CxSP = 1) Max: 125°C + 3 Typical: 25°C Min: -45°C - 3 Max. (125°C) Typical (25°C) Min. (-40°C)  2011-2015 Microchip Technology Inc. DS40001609E-page 374...
  • Page 374 PIC16(L)F1508/9 FIGURE 30-69: COMPARATOR INPUT OFFSET AT 25°C, NORMAL POWER MODE (CxSP = 1), PIC16F1508/9 ONLY Max. Typical Min. Max: Typical + 3 Typical: 25°C Min: Typical - 3 Common Mode Voltage (V)  2011-2015 Microchip Technology Inc. DS40001609E-page 375...
  • Page 375 Min: Typical - 3 (-40°C to +125°C) FIGURE 30-71: LFINTOSC FREQUENCY OVER V AND TEMPERATURE, PIC16F1508/9 ONLY Max. Typical Min. Max: Typical + 3 (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3 (-40°C to +125°C)  2011-2015 Microchip Technology Inc. DS40001609E-page 376...
  • Page 376 Min: Typical - 3 Typical Min. -10% Temperature (°C) HFINTOSC ACCURACY OVER TEMPERATURE, 2.3V  V 5.5V FIGURE 30-73: Max: Typical + 3 Typical: statistical mean Max. Min: Typical - 3 Typical Min. -10% Temperature (°C)  2011-2015 Microchip Technology Inc. DS40001609E-page 377...
  • Page 377 PIC16(L)F1508/9 FIGURE 30-74: SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, PIC16LF1508/9 ONLY Max. Typical Max: 85°C + 3 Typical: 25°C  2011-2015 Microchip Technology Inc. DS40001609E-page 378...
  • Page 378 VREGPM = 1, PIC16F1508/9 ONLY Max. Typical Max: 85°C + 3 Typical: 25°C FIGURE 30-76: SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE, VREGPM = 0, PIC16F1508/9 ONLY Max. Typical Max: 85°C + 3 Typical: 25°C  2011-2015 Microchip Technology Inc. DS40001609E-page 379...
  • Page 379: Development Support

    • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2011-2015 Microchip Technology Inc. DS40001609E-page 380...
  • Page 380 The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process  2011-2015 Microchip Technology Inc. DS40001609E-page 381...
  • Page 381 PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2011-2015 Microchip Technology Inc. DS40001609E-page 382...
  • Page 382 This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2011-2015 Microchip Technology Inc. DS40001609E-page 383...
  • Page 383: Packaging Information

    Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2011-2015 Microchip Technology Inc. DS40001609E-page 384...
  • Page 384 PIC16(L)F1508/9 Package Marking Information (Continued) 20-Lead SSOP (5.30 mm) Example PIC16F1508 -E/SS 1120123 20-Lead QFN (4x4x0.9 mm) Example 20-Lead UQFN (4x4x0.5 mm) PIC16 F1508 PIN 1 PIN 1 E/ML 120123  2011-2015 Microchip Technology Inc. DS40001609E-page 385...
  • Page 385  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%  2011-2015 Microchip Technology Inc. DS40001609E-page 386...
  • Page 386 PIC16(L)F1508/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2015 Microchip Technology Inc. DS40001609E-page 387...
  • Page 387 PIC16(L)F1508/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2015 Microchip Technology Inc. DS40001609E-page 388...
  • Page 388 PIC16(L)F1508/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2015 Microchip Technology Inc. DS40001609E-page 389...
  • Page 389  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  PP SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%  2011-2015 Microchip Technology Inc. DS40001609E-page 390...
  • Page 390 PIC16(L)F1508/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2015 Microchip Technology Inc. DS40001609E-page 391...
  • Page 391  3DFNDJH LV VDZ VLQJXODWHG  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%  2011-2015 Microchip Technology Inc. DS40001609E-page 392...
  • Page 392 PIC16(L)F1508/9 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ  2011-2015 Microchip Technology Inc. DS40001609E-page 393...
  • Page 393 SEATING PLANE (A3) 0.08 C SIDE VIEW 0.10 C A B 0.10 C A B NOTE 1 20X b 0.10 C A B BOTTOM VIEW Microchip Technology Drawing C04-255A Sheet 1 of 2  2011-2015 Microchip Technology Inc. DS40001609E-page 394...
  • Page 394 Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-255A Sheet 2 of 2  2011-2015 Microchip Technology Inc. DS40001609E-page 395...
  • Page 395 Contact Pad Length (X20) 0.80 Contact Pad to Center Pad (X20) 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2255A  2011-2015 Microchip Technology Inc. DS40001609E-page 396...
  • Page 396: Appendix A: Data Sheet Revision History

    Removed Index. Revision D (10/2014) Document re-release. Revision E (10/2015) Added Section 3.2 High-Endurance Flash. Updated Figure 26-1; Registers 4-2, 7-5, and 26-3; Sections 22.4.2, 24.1.5, 26.9.1.2, 26.11.1, and 29.1; and Table 26-2.  2011-2015 Microchip Technology Inc. DS40001609E-page 397...
  • Page 397: The Microchip Website

    Microchip website www.microchip.com. Under “Support”, click “Customer Change Notification” and follow the registration instructions.  2011-2015 Microchip Technology Inc. DS40001609E-page 398...
  • Page 398: Product Identification System

    Tape and Reel option. QTP, SQTP, Code or Special Requirements Pattern: For other small form-factor package (blank otherwise) availability and marking information, please visit www.microchip.com/packaging contact your local sales office.  2011-2015 Microchip Technology Inc. DS40001609E-page 399...
  • Page 399 PIC16(L)F1508/9 NOTES:  2011-2015 Microchip Technology Inc. DS40001609E-page 400...
  • Page 400 ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
  • Page 401 Tel: 886-2-2508-8600 Tel: 631-435-6000 China - Xian Tel: 86-29-8833-7252 Fax: 886-2-2508-0102 San Jose, CA Fax: 86-29-8833-7256 Tel: 408-735-9110 Thailand - Bangkok Tel: 66-2-694-1351 Canada - Toronto Fax: 66-2-694-1350 Tel: 905-673-0699 Fax: 905-673-6509 07/14/15  2011-2015 Microchip Technology Inc. DS40001609E-page 402...
  • Page 402 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Microchip PIC16LF1508-I/SS PIC16F1508-I/ML PIC16F1508-I/P PIC16F1508-I/SO PIC16F1508-I/SS PIC16F1509-I/ML PIC16F1509-I/P PIC16F1509-I/SO PIC16F1509-I/SS PIC16F1508-E/ML PIC16F1508-E/P PIC16F1508-E/SO PIC16F1508-E/SS PIC16F1508T-I/ML PIC16F1508T-I/SO PIC16F1508T-I/SS PIC16F1509-E/ML PIC16F1509-E/P PIC16F1509-E/SO PIC16F1509-E/SS PIC16F1509T-I/ML PIC16F1509T-I/SO PIC16F1509T-I/SS PIC16LF1508- E/ML PIC16LF1508-E/P PIC16LF1508-E/SO PIC16LF1508-E/SS PIC16LF1508-I/ML PIC16LF1508-I/P PIC16LF1508-I/SO PIC16LF1508T-I/ML PIC16LF1508T-I/SO PIC16LF1508T-I/SS PIC16LF1509-E/ML PIC16LF1509-E/P PIC16LF1509-E/SO PIC16LF1509-E/SS PIC16LF1509-I/ML PIC16LF1509-I/P PIC16LF1509-I/SO PIC16LF1509-I/SS PIC16LF1509T-I/ML PIC16LF1509T-I/SO PIC16LF1509T-I/SS PIC16LF1509-E/GZ...

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