Microchip Technology megaAVR 0 Series Manual page 346

Figure 24-15. Quick Command Frame Format
24.3.4.3 TWI Slave Operation
The TWI slave is byte-oriented with optional interrupts after each byte. There are separate slave data and
address/stop interrupt flags. Interrupt flags can also be used for polled operation. There are dedicated
status flags for indicating ACK/NACK received, clock hold, collision, bus error, and read/write direction.
When an interrupt flag is set, the SCL line is forced low. This will give the slave time to respond or handle
data, and will in most cases require software interaction.
The diamond shaped symbols (SW) indicate where software interaction is required.
Figure 24-16. TWI Slave Operation
S1 S3
S2
S
SW Driversoftware
The master provides data
on the bus
Slave provides data on
the bus
Sn
Diagramconnections
The number of interrupts generated is kept to a minimum by automatic handling of most conditions. Quick
command can be enabled to auto-trigger operations and reduce software complexity.
Address Recognition mode can be enabled to allow the slave to respond to all received addresses.
Receiving Address Packets
When the TWI slave is properly configured, it will wait for a Start condition to be detected. When this
happens, the successive address byte will be received and checked by the address match logic, and the
slave will ACK a correct address and store the address in the TWIn.DATA register. If the received address
is not a match, the slave will not acknowledge and store the address, but wait for a new Start condition.
The slave address/stop interrupt flag is set when a Start condition succeeded by a valid address byte is
detected. A general call address will also set the interrupt flag.
A Start condition immediately followed by a Stop condition is an illegal operation and the bus error flag is
set.
The R/W direction flag reflects the direction bit received with the address. This can be read by software to
determine the type of operation currently in progress.
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2018 Microchip Technology Inc.
S
SLAVE ADDRESS INTERRUPT
ADDRESS R
SW
W
SW
Interrupton STOP
SW
ConditionEnabled
Address R/W A P
Figure 24-16
S1
A
A
S2
P
S1 S3
A Sr
A/A DATA
Datasheet Preliminary
®
megaAVR 0-Series
Two-Wire Interface (TWI)
shows the TWI slave operation.
SLAVE DATA INTERRUPT
S2
P
S3
Sr
DATA
SW
A/A
SW
DS40002015A-page 346
A/A