Microchip Technology megaAVR 0 Series Manual page 281

The USART uses three communication lines for data transfer:
• RxD for receiving
• TxD for transmitting
• XCK for the transmission clock in synchronous operation
In addition, the USART has XDIR-Transmit Enable for RS485.
Communication is frame based, and the frame format can be customized to support a wide range of
standards. One frame can be directly followed by a new frame, or the communication line can return to
the idle (high) state. A serial frame consists of:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits (MSB or LSB first)
• Parity bit: Even, odd, or none
• 1 or 2 stop bits
The USART is buffered in both directions, enabling continued data transmission without any delay
between frames. Separate interrupts for receive and transmit completion allow fully interrupt driven
communication. Frame error and buffer overflow are detected in hardware and indicated with separate
status flags. Even or odd parity generation and parity check can also be enabled.
The main functional blocks are the clock generator, the transmitter, and the receiver:
• The clock generator includes a fractional baud rate generator that is able to generate a wide range
of USART baud rates from any system clock frequencies. This removes the need to use an
oscillator with a specific frequency to achieve a required baud rate. It also supports external clock
input in synchronous slave operation.
• The transmitter consists of a single write buffer (DATA), a shift register, and a parity generator. The
write buffer allows continuous data transmission without any delay between frames.
• The receiver consists of a two-level receive buffer (DATA) and a Shift Register. Data and clock
recovery units ensure robust synchronization and noise filtering during asynchronous data
reception. It includes frame error, buffer overflow, and parity error detection.
When the USART is set in one-wire mode, the transmitter and the receiver share the same RxD/TxD (xD)
I/O pin.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit
and receive buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation
are identical in both modes. The registers are used in both modes, but their functionality differs for some
control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse
modulation and demodulation for baud rates up to 115.2 kbps.
The USART can be linked to the Configurable Custom Logic unit (CCL). When used with the CCL, the
RxD data can be decoded before the signal is fed into the USART receiver. TxD data can be encoded
after the signal has been output from the USART transmitter.
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2018 Microchip Technology Inc.
Universal Synchronous and Asynchronous Recei...
Datasheet Preliminary
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megaAVR 0-Series
DS40002015A-page 281