12.4
Register Summary - CPUINT
Offset
Name
Bit Pos.
0x00
CTRLA
0x01
STATUS
0x02
LVL0PRI
0x03
LVL1VEC
12.5
Register Description
©
2018 Microchip Technology Inc.
7:0
IVSEL
7:0
NMIEX
7:0
7:0
CPU Interrupt Controller (CPUINT)
CVT
LVL0PRI[7:0]
LVL1VEC[7:0]
Datasheet Preliminary
®
megaAVR
0-Series
LVL1EX
DS40002015A-page 112
LVL0RR
LVL0EX
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