Microchip Technology megaAVR 0 Series Manual page 60

7.7.3 Status Register
Name: SREG
Offset: 0x0F
Reset: 0x00
Property: -
The Status register contains information about the result of the most recently executed arithmetic or logic
instruction. For details about the bits in this register and how they are affected by the different
instructions, see the Instruction Set Summary.
Bit 7
I
Access
R/W
Reset 0
Bit 7 – I Global Interrupt Enable
Writing a '1' to this bit enables interrupts on the device.
Writing a '0' to this bit disables interrupts on the device, independent of the individual interrupt enable
settings of the peripherals.
This bit is not cleared by hardware after an interrupt has occurred.
This bit can be set and cleared by software with the SEI and CLI instructions.
Changing the I flag through the I/O register results in a one-cycle Wait state on the access.
Bit 6 – T Bit Copy Storage
The bit copy instructions bit load (BLD) and bit store (BST) use the T bit as source or destination for the
operated bit.
A bit from a register in the register file can be copied into this bit by the BST instruction, and this bit can
be copied into a bit in a register in the register file by the BLD instruction.
Bit 5 – H Half Carry Flag
This bit indicates a half carry in some arithmetic operations. Half carry is useful in BCD arithmetic.
Bit 4 – S Sign Bit, S = N ⊕ V
The sign bit (S) is always an exclusive or (xor) between the negative flag (N) and the two's complement
overflow flag (V).
Bit 3 – V Two's Complement Overflow Flag
The two's complement overflow flag (V) supports two's complement arithmetic.
Bit 2 – N Negative Flag
The negative flag (N) indicates a negative result in an arithmetic or logic operation.
Bit 1 – Z Zero Flag
The zero flag (Z) indicates a zero result in an arithmetic or logic operation.
©
2018 Microchip Technology Inc.
6 5
T H
R/W R/W
0 0
4 3
S V
R/W R/W
0 0
Datasheet Preliminary
®
megaAVR 0-Series
AVR CPU
2 1
N Z
R/W R/W
0 0
DS40002015A-page 60
0
C
R/W
0