Microchip Technology megaAVR 0 Series Manual page 162

16.3.2 Interrupts
Table 16-1. Available Interrupt Vectors and Sources
Name Vector Description
VLM Voltage Level Monitor Supply voltage crossing the VLM threshold as configured by VLMCFG in
The VLM interrupt will not be executed if the CPU is halted in debug mode.
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of
the peripheral (peripheral.INTFLAGS).
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral's
Interrupt Control register (peripheral.INTCTRL).
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt
flag is set. The interrupt request remains active until the interrupt flag is cleared. See the peripheral's
INTFLAGS register for details on how to clear interrupt flags.
16.3.3 Sleep Mode Operation
There are two separate fuses defining the BOD configuration in different sleep modes; One fuse defines
the mode used in Active mode and Idle Sleep mode (ACTIVE in FUSE.BODCFG) and is written to the
ACTIVE bits in the Control A register (BOD.CTRLA). The second fuse (SLEEP in FUSE.BODCFG)
selects the mode used in Standby Sleep mode and Power-Down Sleep mode and is loaded into the
SLEEP bits in the Control A register (BOD.CTRLA).
The operating mode in Active mode and Idle Sleep mode (i.e., ACTIVE in BOD.CTRLA) cannot be
altered by software. The operating mode in Standby Sleep mode and Power-Down Sleep mode can be
altered by writing to the SLEEP bits in the Control A register (BOD.CTRLA).
When the device is going into Standby Sleep mode or Power-Down Sleep mode, the BOD will change
operation mode as defined by SLEEP in BOD.CTRLA. When the device is waking up from Standby or
Power-Down Sleep mode, the BOD will operate in the mode defined by the ACTIVE bit field in
BOD.CTRLA.
16.3.4 Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to
these, a certain key must be written to the CPU.CCP register first, followed by a write access to the
protected bits within four CPU instructions.
It is possible to try writing to these registers at any time, but the values are not altered.
The following registers are under CCP:
Table 16-2. Registers Under Configuration Change Protection
Register
SLEEP in BOD.CTRLA
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2018 Microchip Technology Inc.
Conditions
BOD.INTCTRL
Datasheet Preliminary
®
megaAVR 0-Series
Brown-Out Detector (BOD)
Key
IOREG
DS40002015A-page 162