Microchip Technology megaAVR 0 Series Manual page 328

23.5.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -
Bit 7
Access
Reset
Bit 6 – DORD Data Order
Value Description
0 The MSB of the data word is transmitted first
1 The LSB of the data word is transmitted first
Bit 5 – MASTER Master/Slave Select
This bit selects the desired SPI mode.
If SS is configured as input and driven low while this bit is '1', this bit is cleared, and the IF flag in
SPIn.INTFLAGS is set. The user has to write MASTER=1 again to re-enable SPI Master mode.
This behavior is controlled by the Slave Select Disable bit (SSD) in SPIn.CTRLB.
Value Description
0 SPI Slave mode selected
1 SPI Master mode selected
Bit 4 – CLK2X Clock Double
When this bit is written to '1' the SPI speed (SCK frequency, after internal prescaler) is doubled in Master
mode.
Value Description
0 SPI speed (SCK frequency) is not doubled
1 SPI speed (SCK frequency) is doubled in Master mode
Bits 2:1 – PRESC[1:0] Prescaler
This bit field controls the SPI clock rate configured in Master mode. These bits have no effect in Slave
mode. The relationship between SCK and the peripheral clock frequency (f
The output of the SPI prescaler can be doubled by writing the CLK2X bit to '1'.
Value Name
0x0 DIV4
0x1 DIV16
0x2 DIV64
0x3 DIV128
Bit 0 – ENABLE SPI Enable
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2018 Microchip Technology Inc.
6 5
DORD MASTER
R/W R/W
0 0
Serial Peripheral Interface (SPI)
4 3
CLK2X
R/W
0
Description
CLK_PER/4
CLK_PER/16
CLK_PER/64
CLK_PER/128
Datasheet Preliminary
®
megaAVR 0-Series
2 1
PRESC[1:0]
R/W R/W
0 0
) is shown below.
CLK_PER
DS40002015A-page 328
0
ENABLE
R/W
0