Microchip Technology megaAVR 0 Series Manual page 206

19.6.7 Control Register F Clear
Name: CTRLFCLR
Offset: 0x06
Reset: 0x00
Property: -
The individual Status bit can be cleared by writing a '1' to its bit location. This allows each bit to be
cleared without the use of a read-modify-write operation on a single register.
Bit 7
Access
Reset
Bit 3 – CMP2BV Compare 2 Buffer Valid
See CMP0BV.
Bit 2 – CMP1BV Compare 1 Buffer Valid
See CMP0BV.
Bit 1 – CMP0BV Compare 0 Buffer Valid
The CMPnBV bits are set when a new value is written to the corresponding TCAn.CMPnBUF register.
These bits are automatically cleared on an UPDATE condition.
Bit 0 – PERBV Period Buffer Valid
This bit is set when a new value is written to the TCAn.PERBUF register. This bit is automatically cleared
on an UPDATE condition.
©
2018 Microchip Technology Inc.
6 5
16-bit Timer/Counter Type A (TCA)
4 3
CMP2BV CMP1BV
R/W
0
Datasheet Preliminary
®
megaAVR 0-Series
2 1
CMP0BV
R/W R/W
0 0
DS40002015A-page 206
0
PERBV
R/W
0