Microchip Technology megaAVR 0 Series Manual page 304

22.5.5 USART Status Register
Name: STATUS
Offset: 0x04
Reset: 0x00
Property: -
Bit 7
RXCIF
Access R
Reset 0
Bit 7 – RXCIF USART Receive Complete Interrupt Flag
This flag is set to '1' when there is unread data in the receive buffer and cleared when the receive buffer
is empty (i.e. does not contain any unread data). When the receiver is disabled, the receive buffer will be
flushed and consequently, the RXCIF will become zero.
When interrupt-driven data reception is used, the receive complete interrupt routine must read the
received data from RXDATA in order to clear the RXCIF. If not, a new interrupt will occur directly after the
return from the current interrupt.
Bit 6 – TXCIF USART Transmit Complete Interrupt Flag
This flag is set when the entire frame in the Transmit Shift register has been shifted out and there are no
new data in the transmit buffer (TXDATA).
This flag is automatically cleared when the transmit complete interrupt vector is executed. The flag can
also be cleared by writing a '1' to its bit location.
Bit 5 – DREIF USART Data Register Empty Flag
The DREIF indicates if the transmit buffer (TXDATA) is ready to receive new data. The flag is set to '1'
when the transmit buffer is empty and is '0' when the transmit buffer contains data to be transmitted that
has not yet been moved into the Shift register. DREIF is set after a Reset to indicate that the transmitter is
ready. Always write this bit to '0' when writing the STATUS register.
DREIF is cleared to '0' by writing TXDATAL. When interrupt-driven data transmission is used, the Data
Register Empty interrupt routine must either write new data to TXDATA in order to clear DREIF or disable
the Data Register Empty interrupt. If not, a new interrupt will occur directly after the return from the
current interrupt.
Bit 4 – RXSIF USART Receive Start Interrupt Flag
The RXSIF flag indicates a valid Start condition on RxD line. The flag is set when the system is in
standby modes and a high (IDLE) to low (START) valid transition is detected on the RxD line. If the start
detection is not enabled, the RXSIF will always be read as zero. This flag can only be cleared by writing a
'1' to its bit location. This flag is not used in the Master SPI mode operation.
Bit 3 – ISFIF Inconsistent Sync Field Interrupt Flag
This bit is set when the auto-baud is enabled and the sync field bit time is too fast or too slow to give a
valid baud setting. It will also be set when USART is set to LINAUTO mode and the SYNC character differ
from data value 0x55.
Writing a '1' to this bit will clear the flag and bring the USART back to Idle state.
©
2018 Microchip Technology Inc.
Universal Synchronous and Asynchronous Recei...
6 5
TXCIF DREIF
R/W R
0 0
4 3
RXSIF ISFIF
R/W R/W
0 0
Datasheet Preliminary
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megaAVR 0-Series
2 1
BDF
R/W
0
DS40002015A-page 304
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WFB
R/W
0