Microchip Technology megaAVR 0 Series Manual page 339

Figure 24-7 illustrates the master read transaction. The master initiates the transaction by issuing a Start
condition followed by an address packet with the direction bit set to one (ADDRESS+R). The addressed
slave must acknowledge the address for the master to be allowed to continue the transaction.
Figure 24-7. Master Read Transaction
S
Assuming the slave acknowledges the address, the master can start receiving data from the slave. There
are no limitations to the number of data packets that can be transferred. The slave transmits the data
while the master signals ACK or NACK after each data byte. The master terminates the transfer with a
NACK before issuing a Stop condition.
Figure 24-8 illustrates a combined transaction. A combined transaction consists of several read and write
transactions separated by repeated Start conditions (Sr).
Figure 24-8. Combined Transaction
Address Packet #1
S ADDRESS
24.3.2.6 Clock and Clock Stretching
All devices connected to the bus are allowed to stretch the low period of the clock to slow down the
overall clock frequency or to insert Wait states while processing data. A device that needs to stretch the
clock can do this by holding/forcing the SCL line low after it detects a low level on the line.
Three types of clock stretching can be defined, as shown in
Figure 24-9. Clock Stretching
SDA
SCL
Note: Clock stretching is not supported by all I
If a slave device is in Sleep mode and a Start condition is detected, the clock stretching normally works
during the wake-up period. For AVR devices, the clock stretching will be either directly before or after the
ACK/NACK bit, as AVR devices do not need to wake-up for transactions that are not addressed to it.
A slave device can slow down the bus frequency by stretching the clock periodically on a bit level. This
allows the slave to run at a lower system clock frequency. However, the overall performance of the bus
will be reduced accordingly. Both the master and slave device can randomly stretch the clock on a byte
level basis before and after the ACK/NACK bit. This provides time to process incoming or prepare
outgoing data or perform other time-critical tasks.
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2018 Microchip Technology Inc.
Address Packet
ADDRESS R A
N Data Packets
R/W A DATA
Direction
(1)
bit 7 bit 6
S
Wakeup clock
stretching
Transaction
Data Packet
DATA A
N data packets
Transaction
Address Packet #2
A/A Sr ADDRESS
Figure 24-9.
bit 0
Periodic clock
stretching
2
C slaves and masters.
Datasheet Preliminary
®
megaAVR 0-Series
Two-Wire Interface (TWI)
DATA A P
M Data Packets
R/W A DATA
Direction
ACK/NACK
Random clock
stretching
DS40002015A-page 339
A/A P