Register Summary - Tcan In Normal Mode (Splitm In Tcan.ctrld=0) - Microchip Technology megaAVR 0 Series Manual

19.5

Register Summary - TCAn in Normal Mode (SPLITM in TCAn.CTRLD=0)

Offset Name Bit Pos.
0x00 CTRLA
0x01 CTRLB
0x02 CTRLC
0x03 CTRLD
0x04 CTRLECLR
0x05 CTRLESET
0x06 CTRLFCLR
0x07 CTRLFSET
0x08 Reserved
0x09 EVCTRL
0x0A INTCTRL
0x0B INTFLAGS
0x0C
... Reserved
0x0D
0x0E DBGCTRL
0x0F TEMP
0x10
... Reserved
0x1F
0x20 CNT
0x22
... Reserved
0x25
0x26 PER
0x28 CMP0
0x2A CMP1
0x2C CMP2
0x2E
... Reserved
0x35
0x36 PERBUF
0x38 CMP0nBUF
0x3A CMP1nBUF
0x3C CMP2nBUF
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2018 Microchip Technology Inc.
7:0
7:0 CMP2EN
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0 CMP2
7:0 CMP2
7:0
7:0
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
16-bit Timer/Counter Type A (TCA)
CMP1EN CMP0EN ALUPD
CMP2BV
CMP2BV
CMP1 CMP0
CMP1 CMP0
TEMP[7:0]
CNT[7:0]
CNT[15:8]
PER[7:0]
PER[15:8]
CMP[7:0]
CMP[15:8]
CMP[7:0]
CMP[15:8]
CMP[7:0]
CMP[15:8]
PERBUF[7:0]
PERBUF[15:8]
CMPBUF[7:0]
CMPBUF[15:8]
CMPBUF[7:0]
CMPBUF[15:8]
CMPBUF[7:0]
CMPBUF[15:8]
Datasheet Preliminary
®
megaAVR 0-Series
CLKSEL[2:0]
WGMODE[2:0]
CMP2OV CMP1OV
CMD[1:0] LUPD
CMD[1:0] LUPD
CMP1BV CMP0BV
CMP1BV CMP0BV
EVACT[1:0]
DS40002015A-page 197
ENABLE
CMP0OV
SPLITM
DIR
DIR
PERBV
PERBV
CNTEI
OVF
OVF
DBGRUN