Microchip Technology megaAVR 0 Series Manual page 287

Table 22-3. Frame Format Nomenclature
Symbol
St
(n)
P
Sp
IDLE
Parity
Even or odd parity can be selected for error checking by writing the Parity Mode bits (PMODE) in the
Control C register (USARTn.CTRLC). If even parity is selected, the parity bit is set to '1' if the number of
logical one data bits is odd (making the total number of logical ones even). If odd parity is selected, the
parity bit is set to '1' if the number of logical one data bits is even (making the total number of ones odd).
When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares
the result with the parity bit of the corresponding frame. If a parity error is detected, the parity error flag is
set.
SPI Frame Formats
The serial frame in SPI mode is defined to be one character of eight data bits. The USART in master SPI
mode has two valid frame formats:
• 8-bit data, MSb first
• 8-bit data, LSb first
The data order is selected by writing to the Data Order bit (UDORD) in the Control C register
(USARTn.CTRLC).
After a complete frame is transmitted, a new frame can directly follow it, or the communication line can
return to the idle (high) state.
22.3.2.3 Data Transmission - USART Transmitter
When the transmitter has been enabled, the normal port operation of the TxD pin is overridden by the
USART and given the function as the transmitter's serial output. The direction of the pin n must be
configured as output by writing the Direction register for the corresponding port (PORTx.DIR[n]). If the
USART is configured for one-wire operation, the USART will automatically override the RxD/TxD pin to
output, when the transmitter is enabled.
Sending Frames
A data transmission is initiated by loading the Transmit buffer (DATA in USARTn.TXDATA) with the data
to be sent. The data in the transmit buffer is moved to the Shift register when the Shift register is empty
and ready to send a new frame. The Shift register is loaded if it is in Idle state (no ongoing transmission)
or immediately after the last Stop bit of the previous frame is transmitted. When the Shift register is
loaded with data, it will transfer one complete frame.
When the entire frame in the Shift register has been shifted out and there is no new data present in the
transmit buffer, the Transmit Complete Interrupt Flag (TXCIF in USARTn.STATUS) is set and the optional
interrupt is generated.
TXDATA can only be written when the Data Register Empty Flag (DREIF in USARTn.STATUS) is set,
indicating that the register is empty and ready for new data.
©
2018 Microchip Technology Inc.
Universal Synchronous and Asynchronous Recei...
Meaning
Start bit, always low
Data bits (0 to 8)
Parity bit, may be odd or even
Stop bit, always high
No transfer on the communication line (RxD or TxD). The IDLE state is always high
Datasheet Preliminary
®
megaAVR 0-Series
DS40002015A-page 287