Microchip Technology megaAVR 0 Series Manual page 85

9.5.2 Main Clock Control B
Name: MCLKCTRLB
Offset: 0x01
Reset: 0x11
Property: Configuration Change Protection
Bit 7
Access
Reset
Bits 4:1 – PDIV[3:0] Prescaler Division
If the Prescaler Enable (PEN) bit is written to '1', these bits define the division ratio of the main clock
prescaler.
These bits can be written during run-time to vary the clock frequency of the system to suit the application
requirements.
The user software must ensure a correct configuration of input frequency (CLK_MAIN) and prescaler
settings, such that the resulting frequency of CLK_PER never exceeds the allowed maximum (see
Electrical Characteristics).
Value Description
Value Division
0x0 2
0x1 4
0x2 8
0x3 16
0x4 32
0x5 64
0x8 6
0x9 10
0xA 12
0xB 24
0xC 48
other Reserved
Bit 0 – PEN Prescaler Enable
This bit must be written '1' to enable the prescaler. When enabled, the division ratio is selected by the
PDIV bit field.
When this bit is written to '0', the main clock will pass through undivided (CLK_PER=CLK_MAIN),
regardless of the value of PDIV.
©
2018 Microchip Technology Inc.
6 5 4 3
PDIV[3:0]
R/W R/W
1 0
Datasheet Preliminary
®
megaAVR 0-Series
Clock Controller (CLKCTRL)
2 1
R/W R/W
0 0
DS40002015A-page 85
0
PEN
R/W
1