Microchip Technology megaAVR 0 Series Manual page 306

22.5.6 Control A
Name: CTRLA
Offset: 0x05
Reset: 0x00
Property: -
Bit 7
RXCIE
Access R/W
Reset 0
Bit 7 – RXCIE Receive Complete Interrupt Enable
The bit enables the Receive Complete Interrupt (interrupt vector RXC). The enabled interrupt will be
triggered when RXCIF in the USARTn.STATUS register is set.
Bit 6 – TXCIE Transmit Complete Interrupt Enable
This bit enables the Transmit Complete Interrupt (interrupt vector TXC). The enabled interrupt will be
triggered when the TXCIF in the USARTn.STATUS register is set.
Bit 5 – DREIE Data Register Empty Interrupt Enable
This bit enables the Data Register Empty Interrupt (interrupt vector DRE). The enabled interrupt will be
triggered when the DREIF in the USART.STATUS register is set.
Bit 4 – RXSIE Receiver Start Frame Interrupt Enable
Writing a '1' to this bit enables the Start Frame Detector to generate an interrupt on interrupt vector RXC
when a start-of-frame condition is detected.
Bit 3 – LBME Loop-back Mode Enable
Writing this bit to '1' enables an internal connection between the TxD and RxD pin.
Bit 2 – ABEIE Auto-baud Error Interrupt Enable
Writing this bit to '1' enables the auto-baud error interrupt on interrupt vector RXC. The enabled interrupt
will trigger for conditions where the ISFIF flag is set.
Bits 1:0 – RS485[1:0] RS-485 Mode
These bits enable the RS-485 and select the operation mode.
Value Name Description
0x0 OFF
0x1 EXT
0x2 INT
0x3 -
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2018 Microchip Technology Inc.
Universal Synchronous and Asynchronous Recei...
6 5
TXCIE DREIE
R/W R/W
0 0
Disabled.
Enables RS-485 mode with control of an external line driver through a dedicated
Transmit Enable (TE) pin.
Enables RS-485 mode with control of the internal USART transmitter.
Reserved.
4 3
RXSIE LBME
R/W R/W
0 0
Datasheet Preliminary
®
megaAVR 0-Series
2 1
ABEIE RS485[1:0]
R/W R/W
0 0
DS40002015A-page 306
0
R/W
0