Sram Data Memory; Eeprom Data Memory; User Row (Userrow) - Microchip Technology megaAVR 0 Series Manual

The program counter is able to address the whole program memory. The procedure for writing Flash
memory is described in detail in the documentation of the Non-Volatile Memory Controller (NVMCTRL)
peripheral.
The Flash memory is mapped into the data space and is accessible with normal LD/ST instructions. For
LD/ST instructions, the Flash is mapped from address 0x4000. The Flash memory can be read with the
LPM instruction. For the LPM instruction, the Flash start address is 0x0000.
The ATmega3208/3209/4808/4809 has a CRC module that is a master on the bus.
Table 5-1. Physical Properties of Flash Memory
Property
Size
Page size
Number of pages
Start address in Data Space
Start address in Code Space
5.4

SRAM Data Memory

The primary task of the SRAM memory is to store application data. It is not possible to execute code from
SRAM.
Table 5-2. Physical Properties of SRAM
Property
Size
Start address
5.5

EEPROM Data Memory

The primary task of the EEPROM memory is to store nonvolatile application data. The EEPROM memory
supports single byte read and write. The EEPROM is controlled by the Non-Volatile Memory Controller
(NVMCTRL).
Table 5-3. Physical Properties of EEPROM
Property
Size
Page size
Number of pages
Start address
5.6

User Row (USERROW)

In addition to the EEPROM, the ATmega3208/3209/4808/4809 has one extra page of EEPROM memory
that can be used for firmware settings, the User Row (USERROW). This memory supports single byte
©
2018 Microchip Technology Inc.
ATmega320x
32 KB
128 B
256
0x4000
0x0
ATmega320x
4 KB
0x3000
ATmega320x
256B
64B
4
0x1400
Datasheet Preliminary
®
megaAVR 0-Series
Memories
ATmega480x
48 KB
128 B
384
0x4000
0x0
ATmega480x
6 KB
0x2800
ATmega480x
256B
64B
4
0x1400
DS40002015A-page 19