Microchip Technology megaAVR 0 Series Manual page 241

2. Write Compare/Capture register to {CCMPH, CCMPL}.
3. Write 0x0000 to count register.
4. Re-enable the module.
CCMPH is the number of cycles for which the output will be driven high, CCMPL+1 is the period of the
output pulse.
For different capture register values the output values are:
• CCMPL = 0
• CCMPL = 0xFF
• CCMPH = 0
• 0 < CCMPH ≤ 0xFF
• For 0 < CCMPL < 0xFF
• CCMPH = 0
• If 0 < CCMPH ≤ CCMPL
• CCMPH = CCMPL + 1
Figure 20-9. 8-Bit PWM Mode
CCMPL
CCMPH
CNT
BOTTOM
Output
20.3.3.2 Noise Canceler
The noise canceler improves noise immunity by using a simple digital filter scheme. When the noise filter
is enabled, the peripheral monitors the event channel and keeps a record of the last four observed
samples. If four consecutive samples are equal, the input is considered to be stable and the signal is fed
to the edge detector.
When enabled, the noise canceler introduces an additional delay of four system clock cycles between a
change applied to the input and the update of the input compare register.
The noise canceler uses the system clock and is, therefore, not affected by the prescaler.
20.3.3.3 Synchronized with TCAn
TCB can be configured to use the clock (CLK_TCA) of the Timer/Counter type A (TCAn) by writing to the
Clock Select bit field (CLKSEL) in the Control A register (TCBn.CTRLA). In this setting, the TCB will count
on the exact same clock source as selected in TCA.
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2018 Microchip Technology Inc.
Output = 0
Output = 0
Output = 1 for CCMPH cycles, low for the rest of the period
Output = 0
Output = 1 for CCMPH cycles, low for the rest of the period
Output = 1
(CNT == CCMPL) and
output goes high
16-bit Timer/Counter Type B (TCB)
(CNT == CCMPH) and
output goes low
Datasheet Preliminary
®
megaAVR 0-Series
" Interrupt "
DS40002015A-page 241