Microchip Technology megaAVR 0 Series Manual page 376

25.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
The CRCSCAN.CTRLB register contains the mode and source settings for the CRC. It is not writable
when the CRC is busy or when an NMI has been triggered.
Bit 7
Access
Reset
Bits 1:0 – SRC[1:0] CRC Source
The SRC bit field selects which section of the Flash the CRC module should check. To set up section
sizes, refer to the fuse description.
The CRC can be enabled during internal reset initialization to verify Flash sections before letting the CPU
start (see the "Fuses" chapter). If the CRC is enabled during internal reset initialization, the SRC bit field
will read out as FLASH, BOOTAPP, or BOOT when normal code execution starts (depending on the
configuration).
Value Name
0x0 FLASH
0x1 BOOTAPP The CRC is performed on the boot and application code sections of Flash.
0x2 BOOT
0x3 -
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2018 Microchip Technology Inc.
Cyclic Redundancy Check Memory Scan (CRCSCAN...
6 5
Description
The CRC is performed on the entire Flash (boot, application code, and
application data sections).
The CRC is performed on the boot section of Flash.
Reserved.
4 3
Datasheet Preliminary
®
megaAVR 0-Series
2 1
SRC[1:0]
R/W
0
DS40002015A-page 376
0
R/W
0