Microchip Technology PIC24FV16KM204 FAMILY Datasheet
Microchip Technology PIC24FV16KM204 FAMILY Datasheet

Microchip Technology PIC24FV16KM204 FAMILY Datasheet

General purpose, 16-bit flash microcontroller with xlp technology data sheet

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General Purpose, 16-Bit Flash Microcontroller
Analog Peripheral Features
• Up to Two 8-Bit Digital-to-Analog Converters
(DAC):
- Soft Reset disable function allows DAC to
retain its output value through non-V
Resets
- Support for Idle mode
- Support for left and right-justified input data
• Two Operational Amplifiers (Op Amps):
- Differential inputs
- Selectable power/speed levels:
- Low power/low speed
- High power/high speed
• Up to 22-Channel, 10/12-Bit Analog-to-Digital
Converter:
- 100k samples/second at 12-bit conversion
rate (single Sample-and-Hold)
- Auto-scan with Threshold Detect
- Can operate during Sleep
- Dedicated band gap reference and
temperature sensor input
• Up to Three Rail-to-Rail Analog Comparators:
- Programmable reference voltage for
comparators
- Band gap reference input
- Flexible input multiplexing
- Low-power or high-speed selection options
• Charge Time Measurement Unit (CTMU):
- Capacitive measurement, up to 22 channels
- Time measurement down to 200 ps
resolution
- Up to 16 external Trigger pairs
• Internal Temperature Sensor with Dedicated A/D
Converter Input
 2013 Microchip Technology Inc.
PIC24FV16KM204 FAMILY
with XLP Technology Data Sheet
DD
Advance Information
Multiple/Single Capture Compare
Peripheral (MCCP/SCCP) Features
• 16 or 32-Bit Time Base
• 16 or 32-Bit Capture
- 4-Deep Capture Buffer
• 16 or 32-Bit Compare:
- Single Edge Compare modes
- Dual Edge Compare/PWM modes
- Center-Aligned Compare mode
- Variable Frequency Pulse mode
• Fully Asynchronous Operation, Available in
Sleep modes
• Single Output Steerable mode (MCCP only)
• Brush DC Forward and Reverse modes
(MCCP only)
• Half-Bridge with Dead-Time Delay (MCCP only)
• Push-Pull PWM mode (MCCP only)
• Auto-Shutdown with Programmable Source and
Shutdown State
• Programmable Output Polarity
DS33030A-page 1

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Summary of Contents for Microchip Technology PIC24FV16KM204 FAMILY

  • Page 1 - Capacitive measurement, up to 22 channels - Time measurement down to 200 ps resolution - Up to 16 external Trigger pairs • Internal Temperature Sensor with Dedicated A/D Converter Input Advance Information  2013 Microchip Technology Inc. DS33030A-page 1...
  • Page 2 — 3V Devices F16KM204 1.8-3.6 F16KM202 1.8-3.6 F08KM204 1.8-3.6 F08KM202 1.8-3.6 F16KM104 1.8-3.6 — — — F16KM102 1.8-3.6 — — — F08KM102 1.8-3.6 — — — F08KM101 1.8-3.6 — — — Advance Information  2013 Microchip Technology Inc. DS33030A-page 2...
  • Page 3 • Up to Two Single Output Capture/Compare/PWM based on device operating speed (SCCP) modules and up to Three Multiple Output - LPBOR available for re-arming of the POR Capture/Compare/PWM (MCCP) modules Advance Information  2013 Microchip Technology Inc. DS33030A-page 3...
  • Page 4 DDCORE Pin Features PIC24F08KM101 PIC24FVKM08KM101 MCLR/V /RA5 PGC2/CV +/AN0/CN2/RA0 PGD2/CV -/AN1/CN3/RA1 PGD1/AN2/CTCMP/ULPWU/C1IND/OC2A/CN4/RB0 PGC1/AN3/C1INC/CTED12/CN5/RB1 AN4/U1RX/TCKIB/CTED13/CN6/RB2 OSCI/CLKI/AN13/C1INB/CN30/RA2 OSCO/CLKO/AN14/C1INA/CN29/RA3 PGD3/SOSCI/AN15/CLCINA/CN1/RB4 PGC3/SOSCO/SCLKI/AN16/PWRLCLK/CLCINB/CN0/RA4 AN19/U1TX/CTED1/INT0/CN23/RB7 AN19/U1TX/IC1/OC1A/CTED1/INT0/CN23/RB7 AN20/SCL1/U1CTS/OC1B/CTED10/CN22/RB8 AN21/SDA1/T1CK/U1RTS/U1BCLK/IC2/CLC1O/CTED4/CN21/RB9 IC1/OC1A/INT2/CN8/RA6 CAP OR DDCORE AN12/HLVDIN/SCK1/OC1C/CTED2/CN14/RB12 AN12/HLVDIN/SCK1/OC1C/CTED2/INT2/CN14/RB12 AN11/SDO1/OCFB/OC1D/CTPLS/CN13/RB13 /AN10/SDI1/C1OUT/OCFA/CTED5/INT1/CN12/RB14 AN9/REFO/SS1/TCKIA/CTED6/CN11/RB15 Advance Information  2013 Microchip Technology Inc. DS33030A-page 4...
  • Page 5 PGD3/SOSCI/AN15/CLCINA/CN1/RB4 PGC3/SOSCO/SCLKI/AN16/PWRLCLK/CLCINB/CN0/RA4 AN19/U1TX/CTED1/INT0/CN23/RB7 AN19/U1TX/IC1/OC1A/CTED1/INT0/CN23/RB7 AN20/SCL1/U1CTS/OC1B/CTED10/CN22/RB8 AN21/SDA1/T1CK/U1RTS/U1BCLK/IC2/CLC1O/CTED4/CN21/RB9 IC1/OC1A/INT2/CN8/RA6 CAP OR DDCORE AN12/HLVDIN/SCK1/OC1C/CTED2/CN14/RB12 AN12/HLVDIN/SCK1/OC1C/CTED2/INT2/CN14/RB12 AN11/SDO1/OCFB/OC1D/CTPLS/CN13/RB13 /AN10/SDI1/C1OUT/OCFA/CTED5/INT1/CN12/RB14 AN9/REFO/SS1/TCKIA/CTED6/CN11/RB15 MCLR/V /RA5 MCLR/V /RA5 PGC2/CV + /V +/AN0/CN2/RA0 PGC2/CV + /V +/AN0/CN2/RA0 PGD2/CV -/AN1/CN3/RA1 PGD2/CV -/AN1/CN3/RA1 Advance Information  2013 Microchip Technology Inc. DS33030A-page 5...
  • Page 6 PGC3/AN18/ASCL1/SDO2/IC5/OC1F/CLCINB/CN24/RB6 AN19/U1TX/INT0/CN23/RB7 AN19/U1TX/C2OUT/OC1A/INT0/CN23/RB7 AN20/SCL1/U1CTS/C3OUT/OC1B/CTED10/CN22/RB8 AN21/SDA1/T1CK/U1RTS/U1BCLK/IC2/OC4/CLC1O/CTED4/CN21/RB9 SDI2/IC1/OC5/CLC2O/CTED3/CN9/RA7 C2OUT/OC1A/CTED1/INT2/CN8/RA6 CAP OR DDCORE PGD2/SDI1/OC3A/OC1C/CTED11/CN16/RB10 PGC2/SCK1/OC2A/CTED9/CN15/RB11 DAC1OUT/AN12/HLVDIN/SS2/IC3/OC2B/CTED2/CN14/RB12 DAC1OUT/AN12/HLVDIN/SS2/IC3/OC2B/CTED2/INT2/CN14/ RB12 OA1INC/OA2INC/AN11/SDO1/OCFB/OC3B/OC1D/CTPLS/CN13/RB13 DAC2OUT/CV /OA1IND/OA2IND/AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/RB14 DAC2REF+/OA2OUT/AN9/C3INA/REFO/SS1/TCKIA/CTED6/CN11/RB15 Legend: Values in indicate pin function differences between PIC24F(V)XXKM202 and PIC24F(V)XXKM102 devices. Advance Information  2013 Microchip Technology Inc. DS33030A-page 6...
  • Page 7 DAC2REF+/OA2OUT/AN9/C3INA/REFO/SS1/TCKIA/CTED6/CN11/RB15 MCLR/V /RA5 +/DAC1REF+/AN0/C3INC/CN2/RA0 +/DAC1REF+/AN0/C3INC/CTED1/CN2/RA0 -/AN1/CN3/RA1 -/AN1/CN3/RA1 Legend: Values in indicate pin function differences between PIC24F(V)XXKM202 and PIC24F(V)XXKM102 devices. Note 1: Exposed pad on underside of device is connected to V Advance Information  2013 Microchip Technology Inc. DS33030A-page 7...
  • Page 8 39 V function differences between 40 V PIC24F(V)XXKM202 and PIC24F(V)XXKM102 devices. 41 PGD3/AN17/ASDA1/OC1E/CLCINA/CN27/RB5 Note 1: Exposed pad on underside of 42 PGC3/AN18/ASCL1/OC1F/CLCINB/CN24/RB6 device is connected to V 43 AN19/INT0/CN23/RB7 AN19/C2OUT/OC1A/INT0/CN23/RB7 44 AN20/SCL1/U1CTS/C3OUT/OC1B/CTED10/CN22/RB8 Advance Information  2013 Microchip Technology Inc. DS33030A-page 8...
  • Page 9 SDO2/CN25/RC4 SCK2/CN26/RC5 Legend: Values in indicate pin function differences between PIC24F(V)XXKM202 and PIC24F(V)XXKM102 devices. PGD3/AN17/ASDA1/OC1E/CLCINA/CN27/RB5 Note 1: Exposed pad on underside of PGC3/AN18/ASCL1/OC1F/CLCINB/CN24/RB6 device is connected to V AN19/C2OUT/INT0/CN23/RB7 AN19/OC1A/INT0/CN23/RB7 AN20/SCL1/U1CTS/C3OUT/OC1B/CTED10/CN22/RB8 Advance Information  2013 Microchip Technology Inc. DS33030A-page 9...
  • Page 10: Table Of Contents

    Appendix A: Revision History................................323 Index ......................................... 325 The Microchip Web Site ..................................331 Customer Change Notification Service .............................. 331 Customer Support ....................................331 Reader Response ....................................332 Product Identification System................................333 Advance Information  2013 Microchip Technology Inc. DS33030A-page 10...
  • Page 11 When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. Advance Information  2013 Microchip Technology Inc. DS33030A-page 11...
  • Page 12 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 12...
  • Page 13: Device Overview

    PIC24FV16KM204 FAMILY DEVICE OVERVIEW 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FV16KM204 family incor- This document contains device-specific information for porate a range of features that can significantly reduce the following devices: power consumption during operation. Key features •...
  • Page 14 Microchip device. from V The PIC24FV16KM204 family may be thought of as Other Special Features two different device groups, both offering slightly differ- • Communications: The PIC24FV16KM204 family ent sets of features.
  • Page 15 POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 44-Pin QFN/TQFP, 28-Pin 48-Pin UQFN SPDIP/SSOP/SOIC/QFN Advance Information  2013 Microchip Technology Inc. DS33030A-page 15...
  • Page 16 POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 44-Pin 28-Pin 20-Pin QFN/TQFP, SPDIP/SSOP/SOIC/QFN SOIC/SSOP/SPDIP 48-Pin UQFN Advance Information  2013 Microchip Technology Inc. DS33030A-page 16...
  • Page 17 PIC24FV16KM204 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC24FV16KM204 FAMILY Features Operating Frequency DC-32 MHz Program Memory (bytes) Program Memory (instructions) 5632 2816 5632 2816 Data Memory (bytes) 2048 Data EEPROM Memory (bytes) Interrupt Sources (soft vectors/NMI traps) 40 (36/4) Voltage Range 2.0-5.5V...
  • Page 18 POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 44-Pin 28-Pin 20-Pin QFN/TQFP, SPDIP/SSOP/SOIC/QFN SOIC/SSOP/SPDIP 48-Pin UQFN Advance Information  2013 Microchip Technology Inc. DS33030A-page 18...
  • Page 19 PIC24FV16KM204 FAMILY FIGURE 1-1: PIC24FV16KM204 FAMILY GENERAL BLOCK DIAGRAMS Data Bus Interrupt Controller Data Latch PSV and Table Data Access Data RAM Control Block Program Counter Address Stack Repeat PORTA Latch Control Control Logic Logic RA<0:7> Read AGU Address Latch...
  • Page 20 TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION Pin Number Pin Number Function Buffer Description 20-Pin 28-Pin 20-Pin 28-Pin 44-Pin 44-Pin PDIP/ PDIP/ 28-Pin 48-Pin PDIP/ PDIP/ 28-Pin 48-Pin QFN/ QFN/ SSOP/ SSOP/ UQFN SSOP/ SSOP/ UQFN TQFP TQFP SOIC SOIC SOIC...
  • Page 21 TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number Pin Number Function Buffer Description 20-Pin 28-Pin 20-Pin 28-Pin 44-Pin 44-Pin PDIP/ PDIP/ 28-Pin 48-Pin PDIP/ PDIP/ 28-Pin 48-Pin QFN/ QFN/ SSOP/ SSOP/ UQFN SSOP/ SSOP/ UQFN TQFP TQFP SOIC SOIC...
  • Page 22 TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number Pin Number Function Buffer Description 20-Pin 28-Pin 20-Pin 28-Pin 44-Pin 44-Pin PDIP/ PDIP/ 28-Pin 48-Pin PDIP/ PDIP/ 28-Pin 48-Pin QFN/ QFN/ SSOP/ SSOP/ UQFN SSOP/ SSOP/ UQFN TQFP TQFP SOIC SOIC...
  • Page 23 TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number Pin Number Function Buffer Description 20-Pin 28-Pin 20-Pin 28-Pin 44-Pin 44-Pin PDIP/ PDIP/ 28-Pin 48-Pin PDIP/ PDIP/ 28-Pin 48-Pin QFN/ QFN/ SSOP/ SSOP/ UQFN SSOP/ SSOP/ UQFN TQFP TQFP SOIC SOIC...
  • Page 24 TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number Pin Number Function Buffer Description 20-Pin 28-Pin 20-Pin 28-Pin 44-Pin 44-Pin PDIP/ PDIP/ 28-Pin 48-Pin PDIP/ PDIP/ 28-Pin 48-Pin QFN/ QFN/ SSOP/ SSOP/ UQFN SSOP/ SSOP/ UQFN TQFP TQFP SOIC SOIC...
  • Page 25 TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number Pin Number Function Buffer Description 20-Pin 28-Pin 20-Pin 28-Pin 44-Pin 44-Pin PDIP/ PDIP/ 28-Pin 48-Pin PDIP/ PDIP/ 28-Pin 48-Pin QFN/ QFN/ SSOP/ SSOP/ UQFN SSOP/ SSOP/ UQFN TQFP TQFP SOIC SOIC...
  • Page 26 TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number Pin Number Function Buffer Description 20-Pin 28-Pin 20-Pin 28-Pin 44-Pin 44-Pin PDIP/ PDIP/ 28-Pin 48-Pin PDIP/ PDIP/ 28-Pin 48-Pin QFN/ QFN/ SSOP/ SSOP/ UQFN SSOP/ SSOP/ UQFN TQFP TQFP SOIC SOIC...
  • Page 27 TABLE 1-5: PIC24FV16KM204 FAMILY PINOUT DESCRIPTION (CONTINUED) Pin Number Pin Number Function Buffer Description 20-Pin 28-Pin 20-Pin 28-Pin 44-Pin 44-Pin PDIP/ PDIP/ 28-Pin 48-Pin PDIP/ PDIP/ 28-Pin 48-Pin QFN/ QFN/ SSOP/ SSOP/ UQFN SSOP/ SSOP/ UQFN TQFP TQFP SOIC SOIC...
  • Page 28 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 28...
  • Page 29: Guidelines For Getting Started With 16-Bit Microcontrollers

    RECOMMENDED MINIMUM CONNECTIONS STARTED WITH 16-BIT MICROCONTROLLERS Basic Connection Requirements Getting started with the PIC24FV16KM204 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with MCLR development. The following pins must always be connected: PIC24FV16KM204 •...
  • Page 30 In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 µ µ Advance Information  2013 Microchip Technology Inc. DS33030A-page 30...
  • Page 31 ECJ-3YX1C106K 10 µF ±10% -55 to +125ºC Panasonic ECJ-4YB1C106K 10 µF ±10% -55 to +85ºC Murata GRM32DR71C106KA01L 10 µF ±10% -55 to +125ºC Murata GRM31CR61C106KC31L 10 µF ±10% -55 to +85ºC Advance Information  2013 Microchip Technology Inc. DS33030A-page 31...
  • Page 32 Channel Select” (i.e., PGCx/PGDx pins), programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. more information available Microchip development tools connection requirements, refer to Section 26.0 “Development Support”. Advance Information  2013 Microchip Technology Inc. DS33030A-page 32...
  • Page 33 Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ to 10 kΩ resistor to V on unused pins and drive the output to logic low. Advance Information  2013 Microchip Technology Inc. DS33030A-page 33...
  • Page 34 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 34...
  • Page 35: Cpu

    All modes support Register Direct and various Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. Advance Information  2013 Microchip Technology Inc. DS33030A-page 35...
  • Page 36 ALU STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register PSVPAG Program Space Visibility Page Address Register RCOUNT Repeat Loop Counter Register CORCON CPU Control Register Advance Information  2013 Microchip Technology Inc. DS33030A-page 36...
  • Page 37 2 1 0 — — — — — — — — — — — — IPL3 PSV — — CPU Control Register (CORCON) Registers or bits are shadowed for PUSH.S and POP.S instructions. Advance Information  2013 Microchip Technology Inc. DS33030A-page 37...
  • Page 38 The IPLx Status bits are read-only when NSTDIS (INTCON1<15>) = 1. The IPL<2:0> Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. Advance Information  2013 Microchip Technology Inc. DS33030A-page 38...
  • Page 39 Likewise, output • 16-bit unsigned x 16-bit signed data from the ALU can be written to the W register array • 8-bit unsigned x 8-bit unsigned or a data memory location. Advance Information  2013 Microchip Technology Inc. DS33030A-page 39...
  • Page 40 Instruction Description Arithmetic shift right source register by one or more bits. Shift left source register by one or more bits. Logical shift right source register by one or more bits. Advance Information  2013 Microchip Technology Inc. DS33030A-page 40...
  • Page 41: Memory Organization

    Counter (PC) during program execution, or from a table operation or data space remapping, as described in Section 4.3 “Interfacing Program and Data Memory Spaces”. FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FV16KM204 FAMILY DEVICES PIC24F16KM PIC24F08KM 000000h GOTO Instruction...
  • Page 42 PIC24FV16KM204 FAMILY 4.1.1 PROGRAM MEMORY 4.1.3 DATA EEPROM ORGANIZATION In the PIC24FV16KM204 family, the data EEPROM is mapped to the top of the user program memory space, program memory space organized starting at address, 7FFE00, and expanding up to word-addressable blocks. Although it is treated as address, 7FFFFF.
  • Page 43 512 or 1024 words of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FV16KM204 FAMILY DEVICES Address Address 0000h...
  • Page 44 — — — — — 600h — RTCC/Comp — Band Gap — 700h — — System/ NVM/PMD — — — — HLVD Legend: — = No implemented SFRs in this block. Advance Information  2013 Microchip Technology Inc. DS33030A-page 44...
  • Page 45 TABLE 4-3: CPU CORE REGISTERS MAP File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets WREG0...
  • Page 46 TABLE 4-4: ICN REGISTER MAP File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets (1,2) (1,2)
  • Page 47 TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets INTCON1 NSTDIS...
  • Page 48 TABLE 4-6: TIMER1 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets TMR1 100h...
  • Page 49 TABLE 4-8: MCCP1 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets CCP1CON1L 140h...
  • Page 50 TABLE 4-9: MCCP2 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets CCP2CON1L 164h...
  • Page 51 TABLE 4-10: MCCP3 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets CCP3CON1L 188h...
  • Page 52 TABLE 4-11: SCCP4 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets CCP4CON1L 1ACh...
  • Page 53 TABLE 4-12: SCCP5 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets CCP5CON1L 1D0h...
  • Page 54 TABLE 4-13: MSSP1 (I C™/SPI) REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets SSP1BUF...
  • Page 55 TABLE 4-15: UART1 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets U1MODE 220h...
  • Page 56 TABLE 4-17: OP AMP 1 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets AMP1CON...
  • Page 57 TABLE 4-21: PORTA REGISTER MAP (4,5) (4,5) (4,5) (4,5) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets...
  • Page 58 TABLE 4-24: PAD CONFIGURATION REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets PADCFG1 2FCh...
  • Page 59 TABLE 4-25: A/D REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets ADC1BUF0 300h...
  • Page 60 TABLE 4-26: CTMU REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets CTMUCON1L 35Ah...
  • Page 61 TABLE 4-29: COMPARATOR REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets CMSTAT 630h...
  • Page 62 TABLE 4-31: CLOCK CONTROL REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets RCON 740h...
  • Page 63 <Free Word> W15 (after CALL) accesses from the data EA. Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data POP : [--W15] space word. PUSH : [W15++] Advance Information  2013 Microchip Technology Inc. DS33030A-page 63...
  • Page 64 The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. Table operations are not required to be word-aligned. Table Read operations are permitted in the configuration memory space. Advance Information  2013 Microchip Technology Inc. DS33030A-page 64...
  • Page 65 The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are provided; write operations are also valid in the 800000h user memory area. Advance Information  2013 Microchip Technology Inc. DS33030A-page 65...
  • Page 66 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This corresponds FFFFh exactly to the same lower 15 bits of the actual program space address. 800000h Advance Information  2013 Microchip Technology Inc. DS33030A-page 66...
  • Page 67: Flash Program Memory

    Reference Manual”, Section 4. “Program erase block size. Memory” (DS39715). Table Instructions and Flash The PIC24FV16KM204 family of devices contains Programming internal Flash program memory for storing and execut- ing application code. The memory is readable, writable Regardless of the method used, Flash memory and erasable when operating with V over 1.8V.
  • Page 68 All of the Table Write operations are single-word writes (two instruction cycles), because only the buffers are writ- ten. A programming cycle is required for programming each row. Advance Information  2013 Microchip Technology Inc. DS33030A-page 68...
  • Page 69 Available in ICSP™ mode only. Refer to the device programming specification. The address in the Table Pointer decides which rows will be erased. This bit is used only while accessing data EEPROM. Advance Information  2013 Microchip Technology Inc. DS33030A-page 69...
  • Page 70 // with dummy latch write NVMCON = 0x4058; // Initialize NVMCON asm("DISI #5"); // Block all interrupts for next 5 instructions __builtin_write_NVM(); // C30 function to perform unlock // sequence and set WR Advance Information  2013 Microchip Technology Inc. DS33030A-page 70...
  • Page 71 //Perform TBLWT instructions to write necessary number of latches for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++) __builtin_tblwtl(offset, progData[i++]); // Write to address low word __builtin_tblwth(offset, progData[i]); // Write to upper byte offset = offset + 2; // Increment address Advance Information  2013 Microchip Technology Inc. DS33030A-page 71...
  • Page 72 INITIATING A PROGRAMMING SEQUENCE – ‘C’ LANGUAGE CODE // C example using MPLAB C30 asm("DISI #5"); // Block all interrupts for next 5 instructions __builtin_write_NVM(); // Perform unlock sequence and set WR Advance Information  2013 Microchip Technology Inc. DS33030A-page 72...
  • Page 73: Data Eeprom Memory

    ("mov #0x55, W0 \n" "mov W0, NVMKEY \n" "mov #0xAA, W1 \n" "mov W1, NVMKEY \n"); // Perform Write/Erase operations asm volatile ("bset NVMCON, #WR \n" "nop \n" "nop \n"); Advance Information  2013 Microchip Technology Inc. DS33030A-page 73...
  • Page 74 011010 = Erase 8 words 011001 = Erase 4 words 011000 = Erase 1 word 0100xx = Erase entire data EEPROM Programming Operations (when ERASE bit is ‘0’): 0010xx = Write 1 word Advance Information  2013 Microchip Technology Inc. DS33030A-page 74...
  • Page 75 General descriptions TBLPAG AND NVM of each process are provided for users who are not ADDRESS REGISTERS using the XC16 compiler libraries. 24-Bit PM Address xxxxh TBLPAG W Register EA NVMADRU NVMADR Advance Information  2013 Microchip Technology Inc. DS33030A-page 75...
  • Page 76 ("disi #5"); // Disable Interrupts For 5 Instructions __builtin_write_NVM(); // Issue Unlock Sequence & Start Write Cycle while(NVMCONbits.WR=1); // Optional: Poll WR bit to wait for // write sequence to complete Advance Information  2013 Microchip Technology Inc. DS33030A-page 76...
  • Page 77 ("disi #5"); // Disable Interrupts For 5 Instructions __builtin_write_NVM(); // Issue Unlock Sequence & Start Write Cycle while(NVMCONbits.WR=1); // Optional: Poll WR bit to wait for // write sequence to complete Advance Information  2013 Microchip Technology Inc. DS33030A-page 77...
  • Page 78 // Set up a pointer to the EEPROM location to be erased TBLPAG = __builtin_tblpage(&eeData); // Initialize EE Data page pointer offset = __builtin_tbloffset(&eeData); // Initizlize lower word of address data = __builtin_tblrdl(offset); // Write EEPROM data to write latch Advance Information  2013 Microchip Technology Inc. DS33030A-page 78...
  • Page 79: Resets

    Instruction Glitch Filter MCLR Module Sleep or Idle Rise Detect SYSRST BOREN<1:0> Brown-out SBOREN Reset (RCON<13>) SLEEP Enable Voltage Regulator PIC24FV16KMXXX (only) Configuration Mismatch Trap Conflict Illegal Opcode Uninitialized W Register Advance Information  2013 Microchip Technology Inc. DS33030A-page 79...
  • Page 80 If the FWDTENx Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled regardless of the SWDTEN bit setting. This is implemented on PIC24FV16KMXXX parts only; not used on PIC24F16KMXXX devices. Advance Information  2013 Microchip Technology Inc. DS33030A-page 80...
  • Page 81 SLEEP (RCON<3>) PWRSAV #SLEEP Instruction IDLE (RCON<2>) PWRSAV #IDLE Instruction BOR (RCON<1>) POR, BOR — POR (RCON<0>) — Note: All Reset flag bits may be set or cleared by the user software. Advance Information  2013 Microchip Technology Inc. DS33030A-page 81...
  • Page 82 6: If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC, and in such cases, FRC start-up time is valid. Note: For detailed operating frequency and timing specifications, see Section 29.0 “Electrical Characteristics”. Advance Information  2013 Microchip Technology Inc. DS33030A-page 82...
  • Page 83 POR AND LONG OSCILLATOR Brown-out Reset (BOR) START-UP TIMES The PIC24FV16KM204 family devices implement a The oscillator start-up circuitry and its associated delay BOR circuit, which provides the user several timers are not linked to the device Reset delays that configuration and power-saving options.
  • Page 84 POR and BOR bits are reset to ‘0’ in the software immediately after any POR event. If the BOR bit is ‘1’ while POR is ‘0’, it can be reliably assumed that a BOR event has occurred. Advance Information  2013 Microchip Technology Inc. DS33030A-page 84...
  • Page 85: Interrupt Controller

    For example, the interrupt associated with Vector 0 will take priority over interrupts at any other vector address. PIC24FV16KM204 family devices implement non-maskable traps and unique interrupts; these are summarized in Table 8-1. Advance Information  2013 Microchip Technology Inc. DS33030A-page 85...
  • Page 86 Alternate Interrupt Vector Table (AIVT) Interrupt Vector 52 00017Ch Interrupt Vector 53 00017Eh Interrupt Vector 54 000180h — — — Interrupt Vector 116 Interrupt Vector 117 0001FEh Start of Code 000200h Advance Information  2013 Microchip Technology Inc. DS33030A-page 86...
  • Page 87 IFS0<12> IEC0<12> IPC3<2:0> UART2RX – UART2 Receiver 000050h 000150h IFS1<14> IEC1<14> IPC7<10:8> UART2TX – UART2 Transmitter 000052h 000152h IFS1<15> IEC1<15> IPC7<14:12> ULPWU – Ultra Low-Power Wake-up 0000B4h 0001B4h IFS5<0> IEC5<0> IPC20<2:0> Advance Information  2013 Microchip Technology Inc. DS33030A-page 87...
  • Page 88 CPU Interrupt Registers Priority Level, which are latched into the Vector The PIC24FV16KM204 family of devices implements a Number (VECNUM<6:0>) and the Interrupt Level total of 33 registers for the interrupt controller: (ILR<3:0>) bit fields in the INTTREG register. The new Interrupt Priority Level is the priority of the pending •...
  • Page 89 Level. The value in parentheses indicates the Interrupt Priority Level if IPL3 = 1. The IPLx Status bits are read-only when NSTDIS (INTCON1<15>) = 1. Note: Bit 8 and bits 4 through 0 are described in Section 3.0 “CPU”. Advance Information  2013 Microchip Technology Inc. DS33030A-page 89...
  • Page 90 The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. Note: Bit 2 is described in Section 3.0 “CPU”. Advance Information  2013 Microchip Technology Inc. DS33030A-page 90...
  • Page 91 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 91...
  • Page 92 0 = Interrupt is on the positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt is on the negative edge 0 = Interrupt is on the positive edge Advance Information  2013 Microchip Technology Inc. DS33030A-page 92...
  • Page 93 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Advance Information  2013 Microchip Technology Inc. DS33030A-page 93...
  • Page 94 0 = Interrupt request has not occurred bit 0 SI2C1IF: MSSP1 SPI/I C Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Advance Information  2013 Microchip Technology Inc. DS33030A-page 94...
  • Page 95 0 = Interrupt request has not occurred bit 1 SSP2IF: MSSP2 SPI/I C Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 95...
  • Page 96 0 = Interrupt request has not occurred bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 96...
  • Page 97 0 = Interrupt request has not occurred bit 0 CLC1IF: Configurable Logic Cell 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Advance Information  2013 Microchip Technology Inc. DS33030A-page 97...
  • Page 98 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Advance Information  2013 Microchip Technology Inc. DS33030A-page 98...
  • Page 99 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SSP1IE: MSSP1 SPI/I C Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Advance Information  2013 Microchip Technology Inc. DS33030A-page 99...
  • Page 100 0 = Interrupt request is not enabled bit 1 SSP2IE: MSSP2 SPI/I C Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 100...
  • Page 101 0 = Interrupt request is not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 101...
  • Page 102 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 CLC1IE: Configurable Logic Cell 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Advance Information  2013 Microchip Technology Inc. DS33030A-page 102...
  • Page 103 INT0IP<2:0>: External Interrupt 0 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Advance Information  2013 Microchip Technology Inc. DS33030A-page 103...
  • Page 104 CCP3IP<2:0>: Capture Compare 3 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 104...
  • Page 105 CCT2IP<2:0>: Capture Compare 2 Timer Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Advance Information  2013 Microchip Technology Inc. DS33030A-page 105...
  • Page 106 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Advance Information  2013 Microchip Technology Inc. DS33030A-page 106...
  • Page 107 SSP1IP<2:0>: MSSP1 SPI/I C Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Advance Information  2013 Microchip Technology Inc. DS33030A-page 107...
  • Page 108 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Advance Information  2013 Microchip Technology Inc. DS33030A-page 108...
  • Page 109 CCT3IP<2:0>: Capture Compare 3 Timer Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 109...
  • Page 110 CCT4IP<2:0>: Capture Compare 4 Timer Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Advance Information  2013 Microchip Technology Inc. DS33030A-page 110...
  • Page 111 CCT5IP<2:0>: Capture Compare 5 Timer Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 111...
  • Page 112 C Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 112...
  • Page 113 RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 113...
  • Page 114 U1ERIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 114...
  • Page 115 2-0 HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Advance Information  2013 Microchip Technology Inc. DS33030A-page 115...
  • Page 116 CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 116...
  • Page 117 2-0 CLC1IP<2:0>: CLC1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Advance Information  2013 Microchip Technology Inc. DS33030A-page 117...
  • Page 118 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt vector pending is Number 135 • • • 0000001 = Interrupt vector pending is Number 9 0000000 = Interrupt vector pending is Number 8 Advance Information  2013 Microchip Technology Inc. DS33030A-page 118...
  • Page 119 If the ISR is coded in assembly language, it must be termi- nated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. Advance Information  2013 Microchip Technology Inc. DS33030A-page 119...
  • Page 120 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 120...
  • Page 121: Oscillator Configuration

    Low-Power FRC” (DS39726). declaration bits to the expected frequency range. • A Fail-Safe Clock Monitor (FSCM) that detects clock The oscillator system for the PIC24FV16KM204 family failure and permits safe application recovery or of devices has the following features: shutdown.
  • Page 122 • Secondary Oscillator (SOSC) on the SOSCI and more information, see Section 26.1 “Configuration SOSCO pins Bits”). The Primary Oscillator Configuration bits, The PIC24FV16KM204 family devices consist of POSCMD<1:0> (FOSC<1:0>), and the Initial Oscillator two types of secondary oscillator: Select Configuration bits, FNOSC<2:0>...
  • Page 123 This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC = 0), this bit has no effect. Advance Information  2013 Microchip Technology Inc. DS33030A-page 123...
  • Page 124 This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC = 0), this bit has no effect. Advance Information  2013 Microchip Technology Inc. DS33030A-page 124...
  • Page 125 001 = 250 kHz (divide-by-2) – default 000 = 500 kHz (divide-by-1) bit 7-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. Advance Information  2013 Microchip Technology Inc. DS33030A-page 125...
  • Page 126 100000 = Minimum frequency deviation Note 1: Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC tuning range and may not be monotonic. Advance Information  2013 Microchip Technology Inc. DS33030A-page 126...
  • Page 127 Write the appropriate value to the NOSCx bits (OSCCON<10:8>) for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit to initiate the oscillator switch. Advance Information  2013 Microchip Technology Inc. DS33030A-page 127...
  • Page 128 (optional). certain oscillator modes, the device clock in the Invoke an appropriate amount of software delay PIC24FV16KM204 family devices can also be (cycle counting) to allow the selected oscillator configured to provide a reference clock output signal to and/or PLL to start and stabilize.
  • Page 129 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’ Note 1: The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Sleep mode. Advance Information  2013 Microchip Technology Inc. DS33030A-page 129...
  • Page 130 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 130...
  • Page 131: Power-Saving Features

    PIC24FV16KM204 family. Sleep mode includes these features: • The system clock source is shut down. If an The PIC24FV16KM204 family of devices provides the on-chip oscillator is used, it is turned off. ability to manage power consumption by selectively •...
  • Page 132 When the ULPWU module wakes the device from Low-Voltage Detect (LVD) or temperature sensor. Sleep mode, the ULPWUIF bit (IFS5<0>) is set. Soft- ware can check this bit upon wake-up to determine the wake-up source. Advance Information  2013 Microchip Technology Inc. DS33030A-page 132...
  • Page 133 12-9 Unimplemented: Read as ‘0’ bit 8 ULPSINK: ULPWU Current Sink Enable bit 1 = Current sink is enabled 0 = Current sink is disabled bit 7-0 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 133...
  • Page 134 The Retention Regulator, sometimes referred to as the low-voltage regulator, is designed to provide power to The PIC24FV16KM204 family series devices have a the core at a lower voltage than the standard voltage voltage regulator that has the ability to alter regulator, while consuming significantly lower quiescent functionality to provide power savings.
  • Page 135 Idle mode will do so. Using the disable on Idle feature disables the module while in Idle mode, allowing further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications. Advance Information  2013 Microchip Technology Inc. DS33030A-page 135...
  • Page 136 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 136...
  • Page 137: I/O Ports

    Note that register (TRISx) determines whether the pin is an input PIC24FV16KM204 family devices do not or an output. If the data direction bit is a ‘1’, then the pin support Peripheral Pin Select features. is an input. All port pins are defined as inputs after a Reset.
  • Page 138 ANSA<4:0>: Analog Select Control bits 1 = Digital input buffer is not active (use for analog input) 0 = Digital input buffer is active Note 1: The ANSA4 bit is not available on 20-pin devices. Advance Information  2013 Microchip Technology Inc. DS33030A-page 138...
  • Page 139 1 = Digital input buffer is not active (use for analog input) 0 = Digital input buffer is active Note 1: These bits are not implemented in 20-pin devices. These bits are not implemented in 28-pin devices. Advance Information  2013 Microchip Technology Inc. DS33030A-page 139...
  • Page 140 Setting any of the control bits enables the weak The Input Change Notification function of the I/O ports pull-ups for the corresponding pins. The pull-downs are allows the PIC24FV16KM204 family of devices to enabled separately using the CNPD1 and CNPD3 generate interrupt requests to the processor in...
  • Page 141: Timer1

    FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM TECS<1:0> LPRC TCKPS<1:0> SOSCO Prescaler Gate 1, 8, 64, 256 Sync SOSCI SOSCEN TGATE T1CK TGATE Set T1IF Reset TMR1 Sync TSYNC Comparator Equal Advance Information  2013 Microchip Technology Inc. DS33030A-page 141...
  • Page 142 1 = Timer1 clock source is selected by TECS<1:0> 0 = Internal clock (F bit 0 Unimplemented: Read as ‘0’ Note 1: The TECSx bits are valid only when TCS = 1. Advance Information  2013 Microchip Technology Inc. DS33030A-page 142...
  • Page 143: Capture/Compare/Pwm/Timer Modules (Mccp And Sccp)

    MCCP/SCCP modules, refer to the • CCPxCON1H (Register 13-2) “PIC24F Family Reference Manual”. • CCPxCON2L (Register 13-3) PIC24FV16KM204 family devices include several • CCPxCON2H (Register 13-4) Capture/Compare/PWM/Timer base modules, which • CCPxCON3L (Register 13-5) provide the functionality of three different peripherals of •...
  • Page 144 Note that the T32 bit (CCPxCON1L<5>) should be set before the CCPxTMRL or CCPxPRH registers are written to initialize the 32-bit timer. Advance Information  2013 Microchip Technology Inc. DS33030A-page 144...
  • Page 145 Time Base Sources Generator CCPxRB CCPxTMRH Comparator Set CCPxIF CCPxPRH FIGURE 13-4: 32-BIT TIMER MODE Sync/ Trigger SYNC<4:0> Control OC Clock Time Base CCPxTMRH CCPxTMRL Sources Generator Comparator Set CCTxIF CCPxPRH CCPxPRL Advance Information  2013 Microchip Technology Inc. DS33030A-page 145...
  • Page 146 Sources Edge Increment CCPxTMRH/L Detect Rollover Reset OCFA/OCFB Comparator Match Match Event Event Trigger and Fault Logic Trigger and Sync Logic Sync Sources CCPxRB Buffer Rollover/Reset CCPxRB Output Compare Reset Interrupt Advance Information  2013 Microchip Technology Inc. DS33030A-page 146...
  • Page 147 Edge Detect Logic Set CCPxIF Clock IC Clock Interrupt Sources Select Clock Synchronizer Logic Increment Reset Trigger and Trigger and CCPxTMRH/L 4-Level FIFO Buffer Sync Logic Sync Sources CCPxBUFx System Bus Advance Information  2013 Microchip Technology Inc. DS33030A-page 147...
  • Page 148 The auxiliary output is On the PIC24FV16KM204 family of parts, the following intended to connect to other MCCP or SCCP modules, modules have access to the auxiliary output signal:...
  • Page 149 0 = Uses 16-bit time base for timer, single-edge output compare or input capture function bit 4 CCSEL: Capture/Compare Mode Select bit 1 = Input capture peripheral 0 = Output Compare/PWM/Timer peripheral (exact function is selected by the MOD<3:0> bits) Advance Information  2013 Microchip Technology Inc. DS33030A-page 149...
  • Page 150 0010 = 16-Bit/32-Bit Single-Edge mode, drive output low on compare match 0001 = 16-Bit/32-Bit Single-Edge mode, drive output high on compare match 0000 = 16-Bit/32-Bit Timer mode, output functions are disabled Advance Information  2013 Microchip Technology Inc. DS33030A-page 150...
  • Page 151 This control bit has no function in Input Capture modes. This control bit has no function when TRIGEN = 0. Output postscale settings from 1:5 to 1:16 (0100-1111) will result in a FIFO buffer overflow for Input Capture modes. Advance Information  2013 Microchip Technology Inc. DS33030A-page 151...
  • Page 152 CLC2 Output 10010 10011 to 10111 Unused Comparator 1 11000 Comparator 1 11001 Comparator 1 11010 11011 CTMU 11100 11101 and 11110 Unused None; Timer with Auto-Rollover (FFFFh → 0000h) 11111 Advance Information  2013 Microchip Technology Inc. DS33030A-page 152...
  • Page 153 AUTO-SHUTDOWN AND GATING SOURCES ASDGx Bits Auto-Shutdown/Gating Source Comparator 1 Output Comparator 2 Output Comparator 3 Output SCCP4 Output Compare SCCP5 Output Compare CLC1 Output OCFA Fault Input OCFB Fault Input Advance Information  2013 Microchip Technology Inc. DS33030A-page 153...
  • Page 154 011 = Comparator 3 output 010 = Comparator 2 output 001 = Comparator 1 output 000 = Input Capture x (ICx) I/O pin Note 1: OCFEN through OCBEN (bits<13:9>) are implemented in MCCPx modules only. Advance Information  2013 Microchip Technology Inc. DS33030A-page 154...
  • Page 155 000010 = Insert 2 dead-time delay periods between complementary output signals 000001 = Insert 1 dead-time delay period between complementary output signals 000000 = Dead-time logic is disabled Note 1: This register is implemented in MCCPx modules only. Advance Information  2013 Microchip Technology Inc. DS33030A-page 155...
  • Page 156 10 = Pins are driven inactive when a shutdown event occurs 0x = Pins are in a high-impedance state when a shutdown event occurs Note 1: These bits are implemented in MCCPx modules only. Advance Information  2013 Microchip Technology Inc. DS33030A-page 156...
  • Page 157 1 = The Input Capture FIFO buffer has overflowed 0 = The Input Capture FIFO buffer has not overflowed bit 0 ICBNE: Input Capture Buffer Status bit Input Capture buffer has data available Input Capture buffer is empty Advance Information  2013 Microchip Technology Inc. DS33030A-page 157...
  • Page 158 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 158...
  • Page 159: Master Synchronous Serial Port (Mssp)

    C interface supports the following modes in hardware: • Master mode • Multi-Master mode • Slave mode with 10-Bit and 7-Bit Addressing and Address Masking • Byte NACKing • Selectable Address and Data Hold, and Interrupt Masking Advance Information  2013 Microchip Technology Inc. DS33030A-page 159...
  • Page 160 SPI Slave SSPM<3:0> = 010x SDOx SDIx Serial Input Buffer Serial Input Buffer (SSPxBUF) (SSPxBUF) SDIx SDOx Shift Register Shift Register (SSPxSR) (SSPxSR) Serial Clock SCKx SCKx PROCESSOR 1 PROCESSOR 2 Advance Information  2013 Microchip Technology Inc. DS33030A-page 160...
  • Page 161 Write Collision Detect Clock Arbitrate/WCOL Detect SCLx In Clock Arbitration (hold off clock source) Set/Reset S, P (SSPxSTAT), WCOL State Counter for Bus Collision Set SSPxIF, BCLxIF End of XMIT/RCV Reset ACKSTAT, PEN Advance Information  2013 Microchip Technology Inc. DS33030A-page 161...
  • Page 162 BF: Buffer Full Status bit 1 = Receive is complete, SSPxBUF is full 0 = Receive is not complete, SSPxBUF is empty Note 1: Polarity of clock state is set by the CKP bit (SSPxCON1<4>). Advance Information  2013 Microchip Technology Inc. DS33030A-page 162...
  • Page 163 Start bit, Stop bit or not ACK bit. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode. Advance Information  2013 Microchip Technology Inc. DS33030A-page 163...
  • Page 164 Start bit, Stop bit or not ACK bit. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode. Advance Information  2013 Microchip Technology Inc. DS33030A-page 164...
  • Page 165 SSPxBUF register. When enabled, these pins must be properly configured as inputs or outputs. Bit combinations not specifically listed here are either reserved or implemented in I C™ mode only. Advance Information  2013 Microchip Technology Inc. DS33030A-page 165...
  • Page 166 Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. SSPxADD values of 0, 1 or 2 are not supported when the Baud Rate Generator is used with I C mode. Advance Information  2013 Microchip Technology Inc. DS33030A-page 166...
  • Page 167 The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. If the I C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). Advance Information  2013 Microchip Technology Inc. DS33030A-page 167...
  • Page 168 For daisy-chained SPI operation: Allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF. Advance Information  2013 Microchip Technology Inc. DS33030A-page 168...
  • Page 169 This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as enabled. The ACKTIM status bit is active only when the AHEN bit or DHEN bit is set. Advance Information  2013 Microchip Technology Inc. DS33030A-page 169...
  • Page 170 1 = Masking of corresponding bit of SSPxADD is enabled 0 = Masking of corresponding bit of SSPxADD is disabled Note 1: MSK0 is not used as a mask bit in 7-bit addressing. Advance Information  2013 Microchip Technology Inc. DS33030A-page 170...
  • Page 171 1 = The SPI clock (SCK1) of MSSP1 to the pin is disabled 0 = The SPI clock (SCK1) of MSSP1 is output to the pin bit 7-0 Unimplemented: Read as ‘0’ Note 1: These bits are implemented only on PIC24FXXKM20X devices. Advance Information  2013 Microchip Technology Inc. DS33030A-page 171...
  • Page 172 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 172...
  • Page 173: Universal Asynchronous Receiver Transmitter (Uart)

    Status register for either USART1 or 16-Bit Prescaler USART2. FIGURE 15-1: UARTx MODULE SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator ® IrDA UxBCLK Hardware Flow Control UxRTS UxCTS UxRX UARTx Receiver UxTX UARTx Transmitter Advance Information  2013 Microchip Technology Inc. DS33030A-page 173...
  • Page 174 = 9615 Error = (Calculated Baud Rate – Desired Baud Rate) Desired Baud Rate = (9615 – 9600)/9600 = 0.16% Note 1: Based on F /2; Doze mode and PLL are disabled. Advance Information  2013 Microchip Technology Inc. DS33030A-page 174...
  • Page 175 After the Break has been sent, the UTXBRK bit input from the infrared receiver. The transmit pin is reset by hardware. The Sync character now (UxTX) acts as the output to the infrared transmitter. transmits. Advance Information  2013 Microchip Technology Inc. DS33030A-page 175...
  • Page 176 0 = UxRX Idle state is ‘1’ Note 1: This feature is is only available for the 16x BRG mode (BRGH = 0). The bit availability depends on the pin availability. Advance Information  2013 Microchip Technology Inc. DS33030A-page 176...
  • Page 177 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is is only available for the 16x BRG mode (BRGH = 0). The bit availability depends on the pin availability. Advance Information  2013 Microchip Technology Inc. DS33030A-page 177...
  • Page 178 10 = Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer; receive buffer has one or more characters Advance Information  2013 Microchip Technology Inc. DS33030A-page 178...
  • Page 179 RSR to the empty state) bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data; at least one more characters can be read 0 = Receive buffer is empty Advance Information  2013 Microchip Technology Inc. DS33030A-page 179...
  • Page 180 = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 URX8: Data of the Received Character bit (in 9-bit mode) bit 7-0 URX<7:0>: Data of the Received Character bits Advance Information  2013 Microchip Technology Inc. DS33030A-page 180...
  • Page 181: Real-Time Clock And Calendar (Rtcc)

    MTHDY RTCC Timer RTCVAL WKDYHR MINSEC Alarm Event Comparator ALMTHDY Alarm Registers with Masks ALRMVAL ALWDHR ALMINSEC Repeat Counter RTCOUT<1:0> RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Clock Source RTCOE Advance Information  2013 Microchip Technology Inc. DS33030A-page 181...
  • Page 182 ; Restore the original W register values from the stack. EXAMPLE 16-2: SETTING THE RTCWREN BIT IN ‘C’ //This builtin function executes implements the unlock sequence and sets //the RTCWREN bit. __builtin_write_RTCWEN(); Advance Information  2013 Microchip Technology Inc. DS33030A-page 182...
  • Page 183 A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register. Advance Information  2013 Microchip Technology Inc. DS33030A-page 183...
  • Page 184 A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register. Advance Information  2013 Microchip Technology Inc. DS33030A-page 184...
  • Page 185 The RTCPWC register is only affected by a POR. When a new value is written to these register bits, the Seconds Value register should also be written to properly reset the clock prescalers in the RTCC. Advance Information  2013 Microchip Technology Inc. DS33030A-page 185...
  • Page 186 11111111 = Alarm will repeat 255 more times 00000000 = Alarm will not repeat The counter decrements on any alarm event; it is prevented from rolling over from 00h to FFh unless CHIME = 1. Advance Information  2013 Microchip Technology Inc. DS33030A-page 186...
  • Page 187 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN = 1. Advance Information  2013 Microchip Technology Inc. DS33030A-page 187...
  • Page 188 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9. Advance Information  2013 Microchip Technology Inc. DS33030A-page 188...
  • Page 189 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN = 1. Advance Information  2013 Microchip Technology Inc. DS33030A-page 189...
  • Page 190 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9. Advance Information  2013 Microchip Technology Inc. DS33030A-page 190...
  • Page 191 PWCSTAB<7:0> = 00000000, the sample window timer starts counting from every alarm event when PWCEN = 1. Note 1: A write to this register is only allowed when RTCWREN = 1. Advance Information  2013 Microchip Technology Inc. DS33030A-page 191...
  • Page 192 (ALRMEN = 0). It is recommended that • Enabled using the ALRMEN bit the ALCFGRPT register and CHIME bit be (ALCFGRPT<15>) changed when RTCSYNC = 0. • One-time alarm and repeat alarm options are available Advance Information  2013 Microchip Technology Inc. DS33030A-page 192...
  • Page 193 PWC periodicity. (RTCEN = 1), the PWCEN register bit must be set and the RTCC pin must be driving the PWC control signal (RTCOE = 1 and RTCCLK<1:0> = 11). Advance Information  2013 Microchip Technology Inc. DS33030A-page 193...
  • Page 194 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 194...
  • Page 195: Configurable Logic Cell (Clc)

    INTP Sets CLCIN[24] CLCxIF CLCIN[25] INTN Flag CLCIN[26] CLCIN[27] Interrupt CLCIN[28] CLCIN[29] CLCIN[30] CLCIN[31] Figure 17-3 Note: All register bits shown in this figure can be found in the CLCxCONL register. Advance Information  2013 Microchip Technology Inc. DS33030A-page 195...
  • Page 196 1-Input Transparent Latch with S and R Gate 4 Gate 2 Logic Output Gate 2 Logic Output Gate 1 Gate 4 Gate 1 Gate 3 Gate 3 MODE<2:0> = 110 MODE<2:0> = 111 Advance Information  2013 Microchip Technology Inc. DS33030A-page 196...
  • Page 197 Data Gate 4 CLCIN[25] Gate 4 CLCIN[26] (Same as Data Gate 1) Data 4 Non-Inverted CLCIN[27] CLCIN[28] Data 4 Inverted CLCIN[29] CLCIN[30] CLCIN[31] DS4x (CLCxSEL<14:12>) Note: All controls are undefined at power-up. Advance Information  2013 Microchip Technology Inc. DS33030A-page 197...
  • Page 198 LCPOL: CLCx Output Polarity Control bit 1 = The output of the module is inverted 0 = The output of the module is not inverted bit 4-3 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 198...
  • Page 199 G1POL: Gate 1 Polarity Control bit 1 = The output of Channel 1 logic is inverted when applied to the logic cell 0 = The output of Channel 1 logic is not inverted Advance Information  2013 Microchip Technology Inc. DS33030A-page 199...
  • Page 200 000 = CLCINA I/O pin For CLC2: 100 = UART2 RX 011 = SPI2 SDOx 010 = Comparator 2 output 001 = CLC2 output 000 = CLCINA I/O pin bit 7 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 200...
  • Page 201 101 = Digital Logic High 100 = 8 MHz FRC clock source 011 = LPRC clock source 010 = SOSC clock source 001 = System Clock (T 000 = CLCINA I/O pin Advance Information  2013 Microchip Technology Inc. DS33030A-page 201...
  • Page 202 G1D3N: Gate 1 Data Source 3 Negated Enable bit 1 = The Data Source 3 inverted signal is enabled for Gate 1 0 = The Data Source 3 inverted signal is disabled for Gate 1 Advance Information  2013 Microchip Technology Inc. DS33030A-page 202...
  • Page 203 G1D1N: Gate 1 Data Source 1 Negated Enable bit 1 = The Data Source 1 inverted signal is enabled for Gate 1 0 = The Data Source 1 inverted signal is disabled for Gate 1 Advance Information  2013 Microchip Technology Inc. DS33030A-page 203...
  • Page 204 G3D3N: Gate 3 Data Source 3 Negated Enable bit 1 = The Data Source 3 inverted signal is enabled for Gate 3 0 = The Data Source 3 inverted signal is disabled for Gate 3 Advance Information  2013 Microchip Technology Inc. DS33030A-page 204...
  • Page 205 G3D1N: Gate 3 Data Source 1 Negated Enable bit 1 = The Data Source 1 inverted signal is enabled for Gate 3 0 = The Data Source 1 inverted signal is disabled for Gate 3 Advance Information  2013 Microchip Technology Inc. DS33030A-page 205...
  • Page 206 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 206...
  • Page 207: High/Low-Voltage Detect (Hlvd)

    FIGURE 18-1: HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM Externally Generated Trip Point HLVDIN HLVDL<3:0> HLVDEN VDIR HLVDIF – Internal Voltage Reference HLVDEN Advance Information  2013 Microchip Technology Inc. DS33030A-page 207...
  • Page 208 1110 = Trip Point 1 1101 = Trip Point 2 1100 = Trip Point 3 0000 = Trip Point 15 Note 1: For the actual trip point, see Section 27.0 “Electrical Characteristics”. Advance Information  2013 Microchip Technology Inc. DS33030A-page 208...
  • Page 209: 12-Bit A/D Converter With Threshold Detect

    • Selectable Conversion Trigger Source • Fixed-Length (one word per channel), Configurable Conversion Result Buffer • Four Options for Results Alignment • Configurable Interrupt Generation • Operation During CPU Sleep and Idle modes Advance Information  2013 Microchip Technology Inc. DS33030A-page 209...
  • Page 210 AD1CON5 AD1CHS AD1CHITL AD1CHITH AD1CSSL AN20 AD1CSSH AN21 CTMU Temp. Sensor CTMU Sample Control Control Logic Conversion Control Input MUX Control 0.785 * V Pin Config. Control 0.215 * V AVss Advance Information  2013 Microchip Technology Inc. DS33030A-page 210...
  • Page 211 Select the appropriate sample/conversion sequence (AD1CON1<7:4> AD1CON3<12:8>). Configure the MODE12 bit to select A/D resolution (AD1CON1<10>). Select how the conversion results are presented in the buffer (AD1CON1<9:8>). Select the interrupt rate (AD1CON2<6:2>). Advance Information  2013 Microchip Technology Inc. DS33030A-page 211...
  • Page 212 Buffer contents are not cleared when the module is selection of a reference source for differential deactivated with the ADON bit (AD1CON1<15>). sampling. Conversion results and any programmed threshold values are maintained when ADON is set or cleared. Advance Information  2013 Microchip Technology Inc. DS33030A-page 212...
  • Page 213 This version of the TMR1 Trigger allows A/D conversions to be triggered from TMR1 while the device is operating in Sleep mode. The SSRC<3:0> = 0101 option allows conversions to be triggered in Run or Idle modes only. Advance Information  2013 Microchip Technology Inc. DS33030A-page 213...
  • Page 214 This version of the TMR1 Trigger allows A/D conversions to be triggered from TMR1 while the device is operating in Sleep mode. The SSRC<3:0> = 0101 option allows conversions to be triggered in Run or Idle modes only. Advance Information  2013 Microchip Technology Inc. DS33030A-page 214...
  • Page 215 BUFM = 1. The voltage reference setting will not be within the specification with V below 4.5V. The voltage reference setting will not be within the specification with V below 2.3V. Advance Information  2013 Microchip Technology Inc. DS33030A-page 215...
  • Page 216 00000 = 0 T bit 7-0 ADCS<7:0>: A/D Conversion Clock Select bits 11111111-01000000 = Reserved 00111111 = 64 * T    00000001 = 2 * T 00000000 = T Advance Information  2013 Microchip Technology Inc. DS33030A-page 216...
  • Page 217 When using auto-scan with Threshold Detect (ASEN = 1), do not configure the sample clock source to Auto-Convert mode (SSRC<3:0> = 7). Any other available SSRC selection is valid. To use auto-convert as the sample clock source (SSRC<3:0> = 7), make sure ASEN is cleared. Advance Information  2013 Microchip Technology Inc. DS33030A-page 217...
  • Page 218 This is implemented on 28-pin and 44-pin devices only. The band gap value used for this input is 2x or 4x the internal V , which is selected when PVCFG<1:0> = 1x. Advance Information  2013 Microchip Technology Inc. DS33030A-page 218...
  • Page 219 For All Other Values of CM<1:0>: 1 = A match has occurred on A/D Result Channel x 0 = No match has occurred on A/D Result Channel x Note 1: Unimplemented channels are read as ‘0’. Advance Information  2013 Microchip Technology Inc. DS33030A-page 219...
  • Page 220 For All Other Values of CM<1:0>: 1 = A match has occurred on A/D Result Channel n 0 = No match has occurred on A/D Result Channel n Note 1: Unimplemented channels are read as ‘0’. Advance Information  2013 Microchip Technology Inc. DS33030A-page 220...
  • Page 221 1 = Includes corresponding ANx input for scan 0 = Skips channel for input scan Note 1: Unimplemented channels are read as ‘0’. Do not select unimplemented channels for sampling as indeterminate results may be produced. Advance Information  2013 Microchip Technology Inc. DS33030A-page 221...
  • Page 222 CTMEN<15:0>: CTMU Enabled During Conversion bits 1 = CTMU is enabled and connected to the selected channel during conversion 0 = CTMU is not connected to this channel Note 1: Unimplemented channels are read as ‘0’. Advance Information  2013 Microchip Technology Inc. DS33030A-page 222...
  • Page 223 = Sampling Switch Resistance = Sample-and-Hold Capacitance (from DAC) HOLD is negligible if Rs  5 k. Note: The C value depends on the device package and is not tested. The effect of C Advance Information  2013 Microchip Technology Inc. DS33030A-page 223...
  • Page 224 0010 0000 0010 (2050) 0010 0000 0001 (2049) 0010 0000 0000 (2048) 0001 1111 1111 (2047) 0001 1111 1110 (2046) 0001 1111 1101 (2045) 0000 0000 0001 (1) 0000 0000 0000 (0) Voltage Level Advance Information  2013 Microchip Technology Inc. DS33030A-page 224...
  • Page 225 1111 1111 1111 1111  -4095/4096 -4095 1 0000 0000 0001 0000 0000 0000 0000 1111 0000 0000 0001 -4096/4096 -4096 1 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 Advance Information  2013 Microchip Technology Inc. DS33030A-page 225...
  • Page 226 1111 1111 1111 1111  -1023/1024 -1023 100 0000 0001 0000 0000 0000 0000 1111 1110 0000 0001 -1024/1024 -1024 100 0000 0000 0000 0000 0000 0000 1111 1110 0000 0000 Advance Information  2013 Microchip Technology Inc. DS33030A-page 226...
  • Page 227 1111 1111 1110 0000  -1023/1024 0.000 -0.999 100 0000 0001 0000 0000 0000 0000 1000 0000 0010 0000 -1024/1024 0.000 -1.000 100 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 Advance Information  2013 Microchip Technology Inc. DS33030A-page 227...
  • Page 228 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 228...
  • Page 229: 8-Bit Digital-To-Analog Converter (Dac)

    “PIC24F Family Reference Manual”. • Fast settling time, supporting 1 Msps effective sampling rates PIC24FV16KM204 family devices include two 8-bit • Buffered output voltage Digital-to-Analog Converters (DACs) for generating • Three user-selectable voltage reference options analog outputs from digital data.
  • Page 230 0 = DACx output pin is disabled, DACx output is available internally to other peripherals only Note 1: User must also enable Band Gap Buffer 0 (BGBUF0) and set BUFCON<1:0> to ‘00’ to obtain this voltage. Advance Information  2013 Microchip Technology Inc. DS33030A-page 230...
  • Page 231 00 = Reference is not connected (lowest power but no DAC functionality) Note 1: User must also enable Band Gap Buffer 0 (BGBUF0) and set BUFCON<1:0> to ‘00’ to obtain this voltage. Advance Information  2013 Microchip Technology Inc. DS33030A-page 231...
  • Page 232 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 232...
  • Page 233: Dual Operational Amplifier Module

    PIC24FV16KM204 FAMILY 21.0 DUAL OPERATIONAL PIC24FV16KM204 family devices include two opera- tional amplifiers to complement the microcontroller’s AMPLIFIER MODULE other analog features. They may be used to provide analog signal conditioning, either as stand-alone Note: This data sheet summarizes the features of devices or in addition to other analog peripherals.
  • Page 234 010 = Op amp positive input connected to the OAxINC pin 001 = Op amp positive input connected to the OAxINA pin 000 = Op amp positive input connected to AV Advance Information  2013 Microchip Technology Inc. DS33030A-page 234...
  • Page 235: Comparator Module

    FIGURE 22-1: COMPARATOR MODULE BLOCK DIAGRAM CCH<1:0> CREF<1:0> EVPOL<1:0> Trigger/Interrupt CEVT Logic CPOL Input Select Logic C1OUT COUT EVPOL<1:0> Trigger/Interrupt CEVT Logic CPOL C2OUT COUT EVPOL<1:0> Trigger/Interrupt CEVT Logic CPOL C3OUT COUT Advance Information  2013 Microchip Technology Inc. DS33030A-page 235...
  • Page 236 Comparator CxIND > CV Compare Comparator V > CV Compare CON = 1, CREF<1:0> = 11, CCH<1:0> = 11 CON = 1, CREF<1:0> = 10, CCH<1:0> = 10 – – DAC1OUT DAC2OUT CxOUT CxOUT Advance Information  2013 Microchip Technology Inc. DS33030A-page 236...
  • Page 237 01 = Trigger/event/interrupt is generated on the transition of the comparator output If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled bit 5 Unimplemented: Read as ‘0’ Advance Information  2013 Microchip Technology Inc. DS33030A-page 237...
  • Page 238 C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON<8>). bit 0 C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON<8>). Advance Information  2013 Microchip Technology Inc. DS33030A-page 238...
  • Page 239: Comparator Voltage Reference

    CV output. FIGURE 23-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 CVRSS = 0 CVR<3:0> CVREN 32 Steps CVRSS = 1 CVRSS = 0 Advance Information  2013 Microchip Technology Inc. DS33030A-page 239...
  • Page 240 Value Selection 0 ≤ CVR<4:0> ≤ 31 bits When CVRSS = 1: = (V -) + (CVR<4:0>/32) • (V + – V When CVRSS = 0: = (AV ) + (CVR<4:0>/32) • (AV – AV Advance Information  2013 Microchip Technology Inc. DS33030A-page 240...
  • Page 241: Charge Time Measurement Unit (Ctmu)

    CTMU, as well as controlling edge sequencing. CTMUCON2 controls edge source selec- tion and edge source polarity selection. The CTMUICON register selects the current range of current source and trims the current. Advance Information  2013 Microchip Technology Inc. DS33030A-page 241...
  • Page 242 Figure 24-2 displays the external connections used for FIGURE 24-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC24F Device CTMU CTED EDG1STAT Current Source CTED EDG2STAT Output Pulse A/D Converter Advance Information  2013 Microchip Technology Inc. DS33030A-page 242...
  • Page 243 , CTPLS is high. DELAY FIGURE 24-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTMU CTPLS EDG1STAT EDG2STAT EDG1STAT CTED1 Current Source Comparator EDG2STAT – C2INB DELAY Advance Information  2013 Microchip Technology Inc. DS33030A-page 243...
  • Page 244 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current 100010 100001 = Maximum negative change from nominal current Advance Information  2013 Microchip Technology Inc. DS33030A-page 244...
  • Page 245 IRNG<1:0>: Current Source Range Select bits 11 = 100 × Base Current 10 = 10 × Base Current 01 = Base Current Level (0.55 µA nominal) 00 = 1000 × Base Current Advance Information  2013 Microchip Technology Inc. DS33030A-page 245...
  • Page 246 0 = Input is level-sensitive Note 1: Edge sources, CTED7 and CTED8, are not available on 28-pin or 20-pin devices. Edge sources, CTED3, CTED9 and CTED11, are not available on 20-pin devices. Advance Information  2013 Microchip Technology Inc. DS33030A-page 246...
  • Page 247 Unimplemented: Read as ‘0’ Note 1: Edge sources, CTED7 and CTED8, are not available on 28-pin or 20-pin devices. Edge sources, CTED3, CTED9 and CTED11, are not available on 20-pin devices. Advance Information  2013 Microchip Technology Inc. DS33030A-page 247...
  • Page 248 100 = A/D end of conversion signal 011 = SCCP5 auxiliary output 110 = MCCP2 auxiliary output 001 = MCCP1 auxiliary output 000 = No discharge source selected, use the IDISSEN bit Advance Information  2013 Microchip Technology Inc. DS33030A-page 248...
  • Page 249: Special Features

    Table Reads and Table Writes. • Section 33. “Programming and Diagnostics” (DS39716) TABLE 25-1: CONFIGURATION REGISTERS LOCATIONS PIC24FV16KM204 family devices include several features intended to maximize application flexibility and Configuration reliability, and minimize cost through elimination of Address Register external components.
  • Page 250 011 = Primary Oscillator with PLL module (HS+PLL, EC+PLL) 100 = Secondary Oscillator (SOSC) 101 = Low-Power RC Oscillator (LPRC) 110 = 500 kHz Low-Power FRC Oscillator with Divide-by-N (LPFRCDIV) 111 = 8 MHz FRC Oscillator with Divide-by-N (FRCDIV) Advance Information  2013 Microchip Technology Inc. DS33030A-page 250...
  • Page 251 POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary Oscillator mode is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = External Clock mode is selected Advance Information  2013 Microchip Technology Inc. DS33030A-page 251...
  • Page 252 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 Advance Information  2013 Microchip Technology Inc. DS33030A-page 252...
  • Page 253 The MCLRE fuse can only be changed when using the V -based ICSP™ mode entry. This prevents a user from accidentally locking out the device from the low-voltage test entry. Refer to Section 29.0 “Electrical Characteristics” for BOR voltages. Advance Information  2013 Microchip Technology Inc. DS33030A-page 253...
  • Page 254 11 = PGEC1/PGED1 are used for programming and debugging the device 10 = PGEC2/PGED2 are used for programming and debugging the device 01 = PGEC3/PGED3 are used for programming and debugging the device 00 = Reserved; do not use Advance Information  2013 Microchip Technology Inc. DS33030A-page 254...
  • Page 255 ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘0’ bit 15-8 FAMID<7:0>: Device Family Identifier bits 01000101 = PIC24FV16KM204 family bit 7-0 DEV<7:0>: Individual Device Identifier bits 00011111 = PIC24FV16KM204 00011011 = PIC24FV16KM202 00010111 = PIC24FV08KM204...
  • Page 256 -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-4 Unimplemented: Read as ‘0’ bit 3-0 REV<3:0>: Minor Revision Identifier bits Advance Information  2013 Microchip Technology Inc. DS33030A-page 256...
  • Page 257 On-Chip Voltage Regulator FIGURE 25-1: CONNECTIONS FOR THE ON-CHIP REGULATOR All of the PIC24FV16KM204 family devices power their core digital logic at a nominal 3.0V. This may create an Regulator Enabled: issue for designs that are required to operate at a 5.0V...
  • Page 258 Counter 1:1 to 1:32.768 Reset 31 kHz 1 ms/4 ms All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode Advance Information  2013 Microchip Technology Inc. DS33030A-page 258...
  • Page 259 ICD 3, MPLAB REAL ICE™ or PICkit™ 3 is selected as a debugger, the in-circuit debugging For all devices in the PIC24FV16KM204 family, code functionality is enabled. This function allows simple protection for the boot segment is controlled by the debugging functions when used with MPLAB IDE.
  • Page 260 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 260...
  • Page 261: Development Support

    MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. Advance Information  2013 Microchip Technology Inc. DS33030A-page 261...
  • Page 262 • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process Advance Information  2013 Microchip Technology Inc. DS33030A-page 262...
  • Page 263 MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. Advance Information  2013 Microchip Technology Inc. DS33030A-page 263...
  • Page 264 PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. Advance Information  2013 Microchip Technology Inc. DS33030A-page 264...
  • Page 265: Electrical Characteristics

    Absolute maximum ratings for the PIC24FV16KM204 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied.
  • Page 266 PIC24F16KM204 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.60V 3.60V 3.00V 3.00V 1.80V 8 MHz 32 MHz Frequency Note: For frequencies between 8 MHz and 32 MHz, F = 20 MHz * (V – 1.8) + 8 MHz. Advance Information  2013 Microchip Technology Inc. DS33030A-page 266...
  • Page 267 PIC24F16KM204 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED) 3.60V 3.60V 3.00V 3.00V 1.80V 8 MHz 24 MHz Frequency Note: For frequencies between 8 MHz and 24 MHz, F = 13.33 MHz * (V – 1.8) + 8 MHz. Advance Information  2013 Microchip Technology Inc. DS33030A-page 267...
  • Page 268 Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. This is the limit to which V can be lowered without losing RAM data. Advance Information  2013 Microchip Technology Inc. DS33030A-page 268...
  • Page 269 2.05 2.16 (Note 3) Note 1: LPBOR re-arms the POR circuit but does not cause a BOR. This is valid for PIC24F (3.3V) devices. This is valid for PIC24FV (5V) devices. Advance Information  2013 Microchip Technology Inc. DS33030A-page 269...
  • Page 270 1.8V 13.50 55.00 µA 3.3V Legend: Unshaded rows represent PIC24F16KMXXX devices and shaded rows represent PIC24FV16KMXXX devices. Note 1: Oscillator is in External Clock mode (FOSCSEL<2:0> = 010, FOSC<1:0> = 00). Advance Information  2013 Microchip Technology Inc. DS33030A-page 270...
  • Page 271 PIC24F16KMXXX µA 1.8V µA 3.3V Legend: Unshaded rows represent PIC24F16KMXXX devices and shaded rows represent PIC24FV16KMXXX devices. Note 1: Oscillator is in External Clock mode (FOSCSEL<2:0> = 010, FOSC<1:0> = 00). Advance Information  2013 Microchip Technology Inc. DS33030A-page 271...
  • Page 272 PMSLP is set to ‘0’ and WDT, etc., are all switched off. The  current is the additional current consumed when the module is enabled. This current should be added to the base I current. Advance Information  2013 Microchip Technology Inc. DS33030A-page 272...
  • Page 273 PMSLP is set to ‘0’ and WDT, etc., are all switched off. The  current is the additional current consumed when the module is enabled. This current should be added to the base I current. Advance Information  2013 Microchip Technology Inc. DS33030A-page 273...
  • Page 274 Negative current is defined as current sourced by the pin. Refer to Table 1-4 Table 1-5 for I/O pin buffer types. requirements are met when the internal pull-ups are enabled. Advance Information  2013 Microchip Technology Inc. DS33030A-page 274...
  • Page 275 Year Provided no other specifications RETD are violated D135 Supply Current During — — Programming Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Self-write and block erase. Advance Information  2013 Microchip Technology Inc. DS33030A-page 275...
  • Page 276  +125°C for Extended Param Symbol Characteristic Units Conditions VRD310 CV Resolution — — VRD311 CVR Absolute Accuracy — — = 3.3V-5.5V  VRD312 CVR Unit Resistor Value (R) — — Advance Information  2013 Microchip Technology Inc. DS33030A-page 276...
  • Page 277 Nominal value at the center point of the current trim range (CTMUCON1L<7:2> = 000000). On PIC24F16KM parts, the current output is limited to the typical current value when I 4 is chosen. Do not use this current range with a temperature sensing diode. Advance Information  2013 Microchip Technology Inc. DS33030A-page 277...
  • Page 278 Note 1: The op amps use CMOS input circuitry with negligible input bias current. The maximum “effective bias current” is the I/O pin leakage specified by electrical Parameter DI50. Advance Information  2013 Microchip Technology Inc. DS33030A-page 278...
  • Page 279 PIC24FV16KM204 FAMILY 27.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FV16KM204 family AC characteristics and timing parameters. TABLE 27-18: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 1.8V to 3.6V -40°C  T ...
  • Page 280 Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 T ) and high for the Q3-Q4 period (1/2 T Advance Information  2013 Microchip Technology Inc. DS33030A-page 280...
  • Page 281 -40°C  T  +85°C for Industrial Operating temperature -40°C  T  +125°C for Extended Param Characteristic Units Conditions s FRC Start-up Time — — s LPRC Start-up Time — — LPRC Advance Information  2013 Microchip Technology Inc. DS33030A-page 281...
  • Page 282 INTx Pin High or Low Time — — (output) DI40 CNx High or Low Time (input) — — Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Advance Information  2013 Microchip Technology Inc. DS33030A-page 282...
  • Page 283 FIGURE 27-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS MCLR SY12 SY10 Internal PWRT SY11 SYSRST System Clock Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 Advance Information  2013 Microchip Technology Inc. DS33030A-page 283...
  • Page 284 Time PMSLP = 0 s SY72 Low-Voltage Regulator — — Wake-up Time Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. This applies to PIC24FV16KMXXX devices only. Advance Information  2013 Microchip Technology Inc. DS33030A-page 284...
  • Page 285 CCPx Capture or Gating Input Low Time — CCPx Capture or Gating Input High Time — CCPx Capture or Gating Input Period 2 * T — N = prescale value (1, 4 or 16) Advance Information  2013 Microchip Technology Inc. DS33030A-page 285...
  • Page 286 Hold Time of SDIx Data Input to SCKx Edge — SDOx Data Output Rise Time — SDOx Data Output Fall Time — SCKx Output Rise Time (Master mode) — SCKx Output Fall Time (Master mode) — SCKx Frequency — Advance Information  2013 Microchip Technology Inc. DS33030A-page 286...
  • Page 287 SDOx Data Output Fall Time — SCKx Output Rise Time (Master mode) — SCKx Output Fall Time (Master mode) — SDOx Data Output Setup to SCKx Edge — SCKx Frequency — Advance Information  2013 Microchip Technology Inc. DS33030A-page 287...
  • Page 288 SDOx Data Output Valid After SCKx Edge — SSx  After SCKx Edge 1.5 T + 40 — SCKx Frequency — Note 1: Requires the use of Parameter 73A. Only if Parameters are used. Advance Information  2013 Microchip Technology Inc. DS33030A-page 288...
  • Page 289 V SDOx Data Output Valid After SSx  Edge — SSx  After SCKx Edge 1.5 T + 40 — SCKx Frequency — Note 1: Requires the use of Parameter 73A. Only if Parameters are used. Advance Information  2013 Microchip Technology Inc. DS33030A-page 289...
  • Page 290 — Stop Condition 100 kHz mode 4000 — Hold Time 400 kHz mode — FIGURE 27-16: C™ BUS DATA TIMING SCLx SDAx SDAx Note: Refer to Figure 27-5 for load conditions. Advance Information  2013 Microchip Technology Inc. DS33030A-page 290...
  • Page 291 LOW period of the SCLx signal, it must output the next data bit to the SDAx line, max. + T = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification), before the SCLx line is released. Advance Information  2013 Microchip Technology Inc. DS33030A-page 291...
  • Page 292 )(BRG + 1) — — Setup Time 400 kHz mode )(BRG + 1) Stop Condition 100 kHz mode )(BRG + 1) — Hold Time 400 kHz mode )(BRG + 1) — Advance Information  2013 Microchip Technology Inc. DS33030A-page 292...
  • Page 293 SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, Parameter + Parameter = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCLx line is released. Advance Information  2013 Microchip Technology Inc. DS33030A-page 293...
  • Page 294 Note 1: The A/D conversion result never decreases with an increase in the input voltage. Measurements are taken with external V + and V - used as the A/D voltage reference. Advance Information  2013 Microchip Technology Inc. DS33030A-page 294...
  • Page 295 The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (V to V or V to V On the following cycle of the device clock. Advance Information  2013 Microchip Technology Inc. DS33030A-page 295...
  • Page 296 0.5V input overdrive, – 5 no output loading Slew Rate — — V/µs Settling Time — — µs Note 1: DAC output voltage never decreases with an increase in the data code. Advance Information  2013 Microchip Technology Inc. DS33030A-page 296...
  • Page 297: Packaging Information

    In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Advance Information  2013 Microchip Technology Inc. DS33030A-page 297...
  • Page 298 -I/SO XXXXXXXXXXXXXX 1242M7W YYWWNNN 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX PIC24F16KM202 XXXXXXXXXXXXXXXXXXXX -I/SO XXXXXXXXXXXXXXXXXXXX 1242M7W YYWWNNN 28-Lead QFN (6x6 mm) Example PIN 1 PIN 1 24F16KM XXXXXXXX 202-I/ML XXXXXXXX 1242M7W YYWWNNN Advance Information  2013 Microchip Technology Inc. DS33030A-page 298...
  • Page 299 XXXXXXXXXXX 1242M7W YYWWNNN YYWWNNN 44-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX 24FV16KM XXXXXXXXXX 204-I/PT XXXXXXXXXX 1242M7W YYWWNNN 48-Lead UQFN (6x6x0.5 mm) Example PIN 1 PIN 1 XXXXXXXX 24FV16KM XXXXXXXX 204-I/MV YYWWNNN 1242M7W Advance Information  2013 Microchip Technology Inc. DS33030A-page 299...
  • Page 300  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% Advance Information  2013 Microchip Technology Inc. DS33030A-page 300...
  • Page 301  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% Advance Information  2013 Microchip Technology Inc. DS33030A-page 301...
  • Page 302  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  PP SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% Advance Information  2013 Microchip Technology Inc. DS33030A-page 302...
  • Page 303 PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Advance Information  2013 Microchip Technology Inc. DS33030A-page 303...
  • Page 304  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  PP SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% Advance Information  2013 Microchip Technology Inc. DS33030A-page 304...
  • Page 305 PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Advance Information  2013 Microchip Technology Inc. DS33030A-page 305...
  • Page 306 PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Advance Information  2013 Microchip Technology Inc. DS33030A-page 306...
  • Page 307 PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Advance Information  2013 Microchip Technology Inc. DS33030A-page 307...
  • Page 308 PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Advance Information  2013 Microchip Technology Inc. DS33030A-page 308...
  • Page 309 PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Advance Information  2013 Microchip Technology Inc. DS33030A-page 309...
  • Page 310 PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Advance Information  2013 Microchip Technology Inc. DS33030A-page 310...
  • Page 311 PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Advance Information  2013 Microchip Technology Inc. DS33030A-page 311...
  • Page 312 PIC24FV16KM204 FAMILY Advance Information  2013 Microchip Technology Inc. DS33030A-page 312...
  • Page 313 PIC24FV16KM204 FAMILY Advance Information  2013 Microchip Technology Inc. DS33030A-page 313...
  • Page 314 /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ ZLWK  PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ Advance Information  2013 Microchip Technology Inc. DS33030A-page 314...
  • Page 315 PIC24FV16KM204 FAMILY Advance Information  2013 Microchip Technology Inc. DS33030A-page 315...
  • Page 316 PIC24FV16KM204 FAMILY Advance Information  2013 Microchip Technology Inc. DS33030A-page 316...
  • Page 317 PIC24FV16KM204 FAMILY Advance Information  2013 Microchip Technology Inc. DS33030A-page 317...
  • Page 318  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  PP SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% Advance Information  2013 Microchip Technology Inc. DS33030A-page 318...
  • Page 319 PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Advance Information  2013 Microchip Technology Inc. DS33030A-page 319...
  • Page 320 PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Advance Information  2013 Microchip Technology Inc. DS33030A-page 320...
  • Page 321 PIC24FV16KM204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Advance Information  2013 Microchip Technology Inc. DS33030A-page 321...
  • Page 322 PIC24FV16KM204 FAMILY Advance Information  2013 Microchip Technology Inc. DS33030A-page 322...
  • Page 323: Appendix A: Revision History

    PIC24FV16KM204 FAMILY APPENDIX A: REVISION HISTORY Revision A (February 2013) Original data sheet for the PIC24FV16KM204 family of devices. Advance Information  2013 Microchip Technology Inc. DS33030A-page 323...
  • Page 324 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 324...
  • Page 325: Index

    PIC24FV16KM204 FAMILY INDEX Output Compare x ........... 146 PIC24F CPU Core ............. 36 PIC24FV16KM204 Family (General) ......19 Buffer Data Formats ..........225 PSV Operation ............66 Control Registers ............. 212 Reset System ............79 AD1CHITH/L ............ 212 RTCC Module ............181 AD1CHS ............
  • Page 326 PIC24F16KM204 Family ..........15 Environment Software ..........261 PIC24FV16KM104 Family ......... 18 MPLAB PM3 Device Programmer ........264 PIC24FV16KM204 Family ......... 17 MPLAB REAL ICE In-Circuit Emulator System ....263 Device Overview ..............13 MPLINK Object Linker/MPLIB Object Librarian ....262 Core Features ............
  • Page 327 FPOR (Reset Configuration) ........253 Op Amp 1 ..............56 FWDT (Watchdog Timer Configuration) ....252 Op Amp 2 ..............56 HLVDCON (High/Low-Voltage Detect Control) ..208 Pad Configuration ............58 Advance Information  2013 Microchip Technology Inc. DS33030A-page 327...
  • Page 328 Reset, Watchdog Timer. Oscillator Start-up Timer, SSPxMSK (I C Slave Address Mask) ...... 170 Power-up Timer Characteristics ...... 283 SSPxSTAT (MSSPx Status, I C Mode) ....163 SSPxSTAT (MSSPx Status, SPI Mode) ....162 Advance Information  2013 Microchip Technology Inc. DS33030A-page 328...
  • Page 329 SPI Mode (Slave Mode, CKE = 0) ......288 SPI Slave Mode (CKE = 1) ........289 Watchdog Timer (WDT) ........... 257 Windowed Operation ..........258 WWW Address ..............330 WWW, On-Line Support ............ 11 Advance Information  2013 Microchip Technology Inc. DS33030A-page 329...
  • Page 330 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 330...
  • Page 331: The Microchip Web Site

    To register, access the Microchip web site at www.microchip.com. Under “Support”, click “Customer Change Notification” and follow the registration instructions. Advance Information  2013 Microchip Technology Inc. DS33030A-page 331...
  • Page 332: Reader Response

    5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? Advance Information  2013 Microchip Technology Inc. DS33030A-page 332...
  • Page 333: Product Identification System

    SP = SPDIP SO = SOIC SS = SSOP ML = QFN = PDIP = TQFP MV = UQFN Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample Advance Information  2013 Microchip Technology Inc. DS33030A-page 333...
  • Page 334 PIC24FV16KM204 FAMILY NOTES: Advance Information  2013 Microchip Technology Inc. DS33030A-page 334...
  • Page 335 Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH &...
  • Page 336 Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Toronto Fax: 86-29-8833-7256 Fax: 66-2-694-1350 Mississauga, Ontario, Canada China - Xiamen Tel: 905-673-0699 Tel: 86-592-2388138 Fax: 905-673-6509 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 11/29/12 Fax: 86-756-3210049 Advance Information  2013 Microchip Technology Inc. DS33030A-page 336...

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