Functional Description - Microchip Technology megaAVR 0 Series Manual

Value
0x09
0x0A
0x0B
0x0C
Other
Note:
• SPI connections to the CCL work only in master SPI mode
• USART connections to the CCL work only in asynchronous/synchronous USART master mode.
26.3

Functional Description

26.3.1 Initialization
The following bits are enable-protected, meaning that they can only be written when the corresponding
even LUT is disabled (ENABLE=0 in CCL.LUT0CTRLA):
• Sequential Selection (SEQSEL) in Sequential Control 0 register (CCL.SEQCTRL0)
The following registers are enable-protected, meaning that they can only be written when the
corresponding LUT is disabled (ENABLE=0 in CCL.LUT0CTRLA):
• LUT n Control x register, except ENABLE bit (CCL.LUTnCTRLx)
Enable-protected bits in the CCL.LUTnCTRLx registers can be written at the same time as ENABLE in
CCL.LUTnCTRLx is written to '1', but not at the same time as ENABLE is written to '0'.
Enable-protection is denoted by the Enable-Protected property in the register description.
26.3.2 Operation
26.3.2.1 Enabling, Disabling, and Resetting
The CCL is enabled by writing a '1' to the ENABLE bit in the Control register (CCL.CTRLA). The CCL is
disabled by writing a '0' to that ENABLE bit.
Each LUT is enabled by writing a '1' to the LUT Enable bit (ENABLE) in the LUT n Control A register
(CCL.LUTnCTRLA). Each LUT is disabled by writing a '0' to the ENABLE bit in CCL.LUTnCTRLA.
26.3.2.2 Look-Up Table Logic
The look-up table in each LUT unit can generate a combinational logic output as a function of up to three
inputs IN[2:0]. Unused inputs can be masked (tied low). The truth table for the combinational logic
expression is defined by the bits in the CCL.TRUTHn registers. Each combination of the input bits
(IN[2:0]) corresponds to one bit in the TRUTHn register, as shown in the table below.
Table 26-1. Truth Table of LUT
IN[2]
0
0
©
2018 Microchip Technology Inc.
Input source
SPI
TCA0
-
TCB
-
IN[1] IN[0]
0 0
0 1
Datasheet Preliminary
megaAVR
CCL – Configurable Custom Logic
INSEL0 INSEL1
SPI0 MOSI SPI0 MOSI
WO0 WO1
TCB0 WO TCB1 WO
OUT
TRUTH[0]
TRUTH[1]
®
0-Series
INSEL2
SPI0 SCK
WO2
TCB2 WO
DS40002015A-page 380