Microchip Technology megaAVR 0 Series Manual page 210

19.6.11 Interrupt Flag Register - Normal Mode
Name: INTFLAGS
Offset: 0x0B
Reset: 0x00
Property: -
The individual Status bit can be cleared by writing a '1' to its bit location. This allows each bit to be set
without the use of a read-modify-write operation on a single register.
Bit 7
Access
Reset
Bit 6 – CMP2 Compare Channel 2 Interrupt Flag
See CMP0 flag description.
Bit 5 – CMP1 Compare Channel 1 Interrupt Flag
See CMP0 flag description.
Bit 4 – CMP0 Compare Channel 0 Interrupt Flag
The Compare Interrupt flag (CMPn) is set on a compare match on the corresponding compare channel.
For all modes of operation, the CMPn flag will be set when a compare match occurs between the Count
register (TCAn.CNT) and the corresponding Compare register (TCAn.CMPn). The CMPn flag is not
cleared automatically, only by writing a '1' to its bit location.
Bit 0 – OVF Overflow/Underflow Interrupt Flag
This flag is set either on a TOP (overflow) or BOTTOM (underflow) condition, depending on the
WGMODE setting. The OVF flag is not cleared automatically, only by writing a '1' to its bit location.
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2018 Microchip Technology Inc.
6 5
CMP2 CMP1
R/W R/W
0 0
16-bit Timer/Counter Type A (TCA)
4 3
CMP0
R/W
0
Datasheet Preliminary
®
megaAVR 0-Series
2 1
DS40002015A-page 210
0
OVF
R/W
0