Microchip Technology megaAVR 0 Series Manual page 383

I/O Pin Inputs (IO)
When selecting the IO option, the LUT input will be connected to its corresponding I/O pin. Refer to the
I/O Multiplexing section in the Data Sheet for more details about where the LUTnINy pins are located.
Figure 26-4. I/O Pin Input Selection
Peripherals
The different peripherals on the three input lines of each LUT are selected by writing to the respective
LUT n Input y bit fields in the LUT n Control B and C registers:
• INSEL0 in CCL.LUTnCTRLB
• INSEL1 in CCL.LUTnCTRLB
• INSEL2 in CCL.LUTnCTRLC.
26.3.2.4 Filter
By default, the LUT output is a combinational function of the LUT inputs. This may cause some short
glitches when the inputs change the value. These glitches can be removed by clocking through filters if
demanded by application needs.
The Filter Selection bits (FILTSEL) in the LUT Control registers (CCL.LUTnCTRLA) define the digital filter
options. When a filter is enabled, the output will be delayed by two to five CLK cycles (peripheral clock or
alternative clock). One clock cycle after the corresponding LUT is disabled, all internal filter logic is
cleared.
Figure 26-5. Filter
CLK_MUX_OUT
26.3.2.5 Edge Detector
The edge detector can be used to generate a pulse when detecting a rising edge on its input. To detect a
falling edge, the TRUTH table should be programmed to provide inverted output.
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2018 Microchip Technology Inc.
Input
D Q D
R
CLR
CCL – Configurable Custom Logic
Q D Q
R R
Datasheet Preliminary
®
megaAVR 0-Series
FILTSEL
OUT
G
D Q
R
DS40002015A-page 383