=
CLK_PER
PER+1
PWM_SS
Dual-Slope PWM
For dual-slope PWM generation, the period (T) is controlled by TCAn.PER, while the values of
TCAn.CMPn control the duty-cycle of the WG output.
The figure below shows how for dual-slope PWM the counter counts repeatedly from BOTTOM to TOP
and then from TOP to BOTTOM. The waveform generator output is set on BOTTOM, cleared on compare
match when up-counting, and set on compare match when down-counting.
Figure 19-11. Dual-Slope Pulse-Width Modulation
CNT
BOTTOM
Waveform Output WOn
Using dual-slope PWM results in a lower maximum operation frequency compared to the single-slope
PWM operation.
The period register (TCAn.PER) defines the PWM resolution. The minimum resolution is 2 bits
(TCAn.PER=0x0003), and the maximum resolution is 16 bits (TCAn.PER=MAX).
log PER+1
The following equation calculates the exact resolution for dual-slope PWM (R
=
log 2
PWM_DS
The PWM frequency depends on the period setting (TCAn.PER), the peripheral clock frequency
(f
), and the prescaler divider used (CLKSEL in TCAn.CTRLA). It is calculated by the following
CLK_PER
equation:
=
CLK_PER
2 ⋅ PER
PWM_DS
N represents the prescaler divider used.
Port Override for Waveform Generation
To make the waveform generation available on the port pins, the corresponding port pin direction must be
set as output (PORTx.DIR[n]=1). The TCA will override the port pin values when the compare channel is
enabled (CMPnEN=1 in TCAn.CTRLB) and a Waveform Generation mode is selected.
The figure below shows the port override for TCA. The timer/counter compare channel will override the
port pin output value (OUT) on the corresponding port pin. Enabling inverted I/O on the port pin
(INVEN=1 in PORT.PINn) inverts the corresponding WG output.
Figure 19-12. Port Override for Timer/Counter Type A
Waveform
©
2018 Microchip Technology Inc.
Period (T)
MAX
CMPn
TOP
OUT
CMPnEN
Datasheet Preliminary
megaAVR
16-bit Timer/Counter Type A (TCA)
CMPn=BOTTOM
CMPn=TOP
PWM_DS
INVEN
®
0-Series
"update"
"match"
):
WOn
DS40002015A-page 192
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