Microchip Technology megaAVR 0 Series Manual page 341

Figure 24-11. Clock Synchronization
DEVICE1_SCL
DEVICE2_SCL
SCL
(wired-AND)
A high-to-low transition on the SCL line will force the line low for all masters on the bus, and they will start
timing their low clock period. The timing length of the low clock period can vary among the masters.
When a master (DEVICE1 in this case) has completed its low period, it releases the SCL line. However,
the SCL line will not go high until all masters have released it. Consequently, the SCL line will be held low
by the device with the longest low period (DEVICE2). Devices with shorter low periods must insert a wait
state until the clock is released. All masters start their high period when the SCL line is released by all
devices and has gone high. The device, which first completes its high period (DEVICE1), forces the clock
line low, and the procedure is then repeated. The result is that the device with the shortest clock period
determines the high period, while the low period of the clock is determined by the device with the longest
clock period.
24.3.3 TWI Bus State Logic
The bus state logic continuously monitors the activity on the TWI bus lines when the master is enabled. It
continues to operate in all Sleep modes, including power-down.
The bus state logic includes Start and Stop condition detectors, collision detection, inactive bus time-out
detection, and a bit counter. These are used to determine the bus state. The software can get the current
bus state by reading the Bus State bits in the master STATUS register. The bus state can be unknown,
idle, busy, or owner, and is determined according to the state diagram shown in
of the Bus State bits according to state, are shown in binary in the figure below.
©
2018 Microchip Technology Inc.
Low Period Wait
Count State
Datasheet Preliminary
megaAVR
Two-Wire Interface (TWI)
High Period
Count
®
0-Series
Figure 24-12. The values
DS40002015A-page 341