Microchip Technology megaAVR 0 Series Manual page 357

3. Writing to the TWIn.MDATA register.
4. Reading the TWIn.DATA register while the ACKACT control bits in TWIn.MCTRLB are set to either
send ACK or NACK.
5. Writing a valid command to the TWIn.MCTRLB register.
Bit 4 – RXACK Received Acknowledge
This bit is read-only and contains the most recently received Acknowledge bit from the slave. When read
as zero, the most recent acknowledge bit from the slave was ACK. When read as one, the most recent
acknowledge bit was NACK.
Bit 3 – ARBLOST Arbitration Lost
If read as '1' this bit indicates that the master has lost arbitration while transmitting a high data or NACK
bit, or while issuing a Start or repeated Start condition (S/Sr) on the bus.
Writing a '1' to it will clear the ARBLOST flag. However, normal use of the TWI does not require the flag to
be cleared by this method. However, as for the CLKHOLD flag, clearing the ARBLOST flag is not required
during normal use of the TWI.
Clearing the ARBLOST bit will follow the same software interaction as the CLKHOLD flag.
Given the condition where the bus ownership is lost to another master, the software must either abort
operation or resend the data packet. Either way, the next required software interaction is in both cases to
write to the TWIn.MADDR register. A write access to the TWIn.MADDR register will then clear the
ARBLOST flag.
Bit 2 – BUSERR Bus Error
The BUSERR flag indicates that an illegal bus condition has occurred. An illegal bus condition is detected
if a protocol violating Start (S), repeated Start (Sr), or Stop (P) is detected on the TWI bus lines. A Start
condition directly followed by a Stop condition is one example of protocol violation.
Writing a '1' to this bit will clear the BUSERR. However, normal use of the TWI does not require the
BUSERR to be cleared by this method.
A robust TWI driver software design will treat the bus error flag similarly to the ARBLOST flag, assuming
the bus ownership is lost when the bus error flag is set. As for the ARBLOST flag, the next software
operation of writing the TWIn.MADDR register will consequently clear the BUSERR flag. For bus error to
be detected, the bus state logic must be enabled and the system frequency must be 4x the SCL
frequency.
Bits 1:0 – BUSSTATE[1:0] Bus State
These bits indicate the current TWI bus state as defined in the table below. After a System Reset or re-
enabling, the TWI master bus state will be unknown. The change of bus state is dependent on bus
activity.
Writing 0x1 to the BUSSTATE bits forces the bus state logic into its Idle state. However, the bus state
logic cannot be forced into any other state. When the master is disabled, the bus state is 'unknown'.
Value Name
0x0 UNKNOWN
0x1 IDLE
0x2 OWNER
0x3 BUSY
©
2018 Microchip Technology Inc.
Description
Unknown bus state
Bus is idle
This TWI controls the bus
The bus is busy
Datasheet Preliminary
®
megaAVR 0-Series
Two-Wire Interface (TWI)
DS40002015A-page 357