Microchip Technology megaAVR 0 Series Manual page 477

Operan
Mnemonic Description
ds
ROL Rd Rotate Left Through Carry
ROR Rd Rotate Right Through Carry
ASR Rd Arithmetic Shift Right
SWAP Rd Swap Nibbles
SBI A, b Set Bit in I/O Register
CBI A, b Clear Bit in I/O Register
BST Rr, b Bit Store from Register to T
BLD Rd, b Bit load from T to Register
BSET s Flag Set
BCLR s Flag Clear
SEC Set Carry
CLC Clear Carry
SEN Set Negative Flag
CLN Clear Negative Flag
SEZ Set Zero Flag
CLZ Clear Zero Flag
SEI Global Interrupt Enable
CLI Global Interrupt Disable
SES Set Signed Test Flag
CLS Clear Signed Test Flag
SEV Set Two's Complement Overflow
CLV Clear Two's Complement Overflow
SET Set T in SREG
CLT Clear T in SREG
SEH Set Half Carry Flag in SREG
CLH Clear Half Carry Flag in SREG
Table 30-10. MCU Control Instructions
Mnemonic Operands
BREAK
NOP
©
2018 Microchip Technology Inc.
Description Operation
Break (See also in Debug
interface description)
No Operation
Datasheet Preliminary
megaAVR
Instruction Set Summary
Op
Rd(0)
Rd(0) ← C
Rd(n+1) ← Rd(n), n=0..6
C ← Rd(7)
Rd(7) ← C
Rd(n) ← Rd(n+1), n=0..6
C ← Rd(0)
Rd(n) ← Rd(n+1), n=0..6
C ← Rd(0)
Rd(7) ← Rd(7)
Rd(3..0) ↔ Rd(7..4)
I/O(A, b) ← 1
I/O(A, b) ← 0
T ← Rr(b)
Rd(b) ← T
SREG(s) ← 1
SREG(s) ← 0
C ← 1
C ← 0
N ← 1
N ← 0
Z ← 1
Z ← 0
I ← 1
I ← 0
S ← 1
S ← 0
V ← 1
V ← 0
T ← 1
T ← 0
H ← 1
H ← 0
Flags
None
None
®
0-Series
#Clock
Flags
s
Z,C,N,V,H 1
Z,C,N,V 1
Z,C,N,V 1
None 1
None 1
None 1
T 1
None 1
SREG(s) 1
SREG(s) 1
C 1
C 1
N 1
N 1
Z 1
Z 1
I 1
I 1
S 1
S 1
V 1
V 1
T 1
T 1
H 1
H 1
#Clocks
1
1
DS40002015A-page 477