Microchip Technology megaAVR 0 Series Manual page 254

20.5.10 Capture/Compare
Name: CCMP
Offset: 0x0C
Reset: 0x00
Property: -
The TCBn.CCMPL and TCBn.CCMPH register pair represents the 16-bit value TCBn.CCMP. The low
byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at
offset + 0x01.
This register has different functions depending on the mode of operation:
• For capture operation, these registers contain the captured value of the counter at the time the
capture occurs
• In periodic interrupt/time-out and Single-Shot mode, this register acts as the TOP value
• In 8-bit PWM mode, TCBn.CCMPL and TCBn.CCMPH act as two independent registers
Bit 15
Access R/W
Reset 0
Bit 7
Access R/W
Reset 0
Bits 15:8 – CCMP[15:8] Capture/Compare Value High Byte
These bits hold the MSB of the 16-bit compare, capture, and top value.
Bits 7:0 – CCMP[7:0] Capture/Compare Value Low Byte
These bits hold the LSB of the 16-bit compare, capture, and top value.
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2018 Microchip Technology Inc.
14 13
R/W R/W
0 0
6 5
R/W R/W
0 0
16-bit Timer/Counter Type B (TCB)
12 11
CCMP[15:8]
R/W R/W
0 0
4 3
CCMP[7:0]
R/W R/W
0 0
Datasheet Preliminary
®
megaAVR 0-Series
10 9
R/W R/W
0 0
2 1
R/W R/W
0 0
DS40002015A-page 254
8
R/W
0
0
R/W
0