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TMS320C2801 Data
Texas Instruments TMS320C2801 Data Manuals
Manuals and User Guides for Texas Instruments TMS320C2801 Data. We have
1
Texas Instruments TMS320C2801 Data manual available for free PDF download: Data Manual
Texas Instruments TMS320C2801 Data Data Manual (147 pages)
Digital Signal Processors
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 1.55 MB
Table of Contents
Table of Contents
2
F280X, F2801X, C280X Dsps
8
Features
8
Getting Started
9
Introduction
10
Hardware Features (100-Mhz Devices)
11
Hardware Features (60-Mhz Devices)
12
Pin Assignments
13
TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View)
14
TMS320F2806 100-Pin PZ LQFP (Top View)
15
TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP (Top View)
16
Tms320F2801X 100-Pin PZ LQFP (Top View)
17
Tms320F2809, Tms320F2808, Tms320F2806,Tms320F2802, Tms320F2801
17
Tms320F28016, Tms320F28015, Tms320C2802, Tms320C2801
17
100-Ball GGM and ZGM Microstar BGA™ (Bottom View)
17
Signal Descriptions
18
Functional Overview
24
Memory Maps
25
Functional Block Diagram
25
F2809 Memory Map
26
F2808 Memory Map
27
F2806 Memory Map
28
F2802, C2802 Memory Map
29
F2801, F28015, F28016, C2801 Memory Map
29
Addresses of Flash Sectors in F2809
30
Addresses of Flash Sectors in F2808
30
Addresses of Flash Sectors in F2806, F2802
30
Addresses of Flash Sectors in F2801, F28015, F28016
31
Impact of Using the Code Security Module
31
Wait-States
32
Brief Descriptions
33
C28X CPU
33
Memory Bus (Harvard Bus Architecture)
33
Peripheral Bus
33
Real-Time JTAG and Analysis
34
Flash
34
Rom
34
M0, M1 Sarams
34
L0, L1, H0 Sarams
35
Boot ROM
35
Boot Mode Selection
35
Security
36
Peripheral Interrupt Expansion (PIE) Block
37
External Interrupts (XINT1, XINT2, XNMI)
37
Oscillator and PLL
37
Watchdog
37
Peripheral Clocking
37
Low-Power Modes
37
Peripheral Frames 0, 1, 2 (Pfn)
38
General-Purpose Input/Output (GPIO) Multiplexer
38
32-Bit CPU-Timers (0, 1, 2)
38
Control Peripherals
38
Serial Port Peripherals
39
Register Map
39
Peripheral Frame 0 Registers
40
Peripheral Frame 1 Registers
40
Device Emulation Registers
41
Interrupts
41
Peripheral Frame 2 Registers
41
System Control
41
External and PIE Interrupt Sources
43
Multiplexing of Interrupts Using the PIE Block
43
PIE Peripheral Interrupts
43
External Interrupts
44
PIE Configuration and Control Registers
44
External Interrupt Registers
44
System Control
45
Clock and Reset Domains
45
OSC and PLL Block
46
OSC and PLL Block Diagram
46
PLL, Clocking, Watchdog, and Low-Power Mode Registers
46
External Reference Oscillator Clock Option
47
Using a 3.3-V External Oscillator
47
Using a 1.8-V External Oscillator
47
Using the Internal Oscillator
47
PLL-Based Clock Module
48
PLLCR Register Bit Definitions
48
Loss of Input Clock
49
Possible PLL Configuration Modes
49
Watchdog Block
50
Watchdog Module
50
Low-Power Modes Block
51
Low-Power Modes
51
Peripherals
52
32-Bit CPU-Timers 0/1/2
52
CPU-Timers
52
CPU-Timer Interrupt Signals and Output Signal
53
CPU-Timers 0, 1, 2 Configuration and Control Registers
53
Enhanced PWM Modules (Epwm1/2/3/4/5/6)
54
Multiple PWM Modules in a 280X System
54
Epwm Control and Status Registers
55
Epwm Sub-Modules Showing Critical Internal Signal Interconnections
56
Hi-Resolution PWM (HRPWM)
57
Enhanced CAP Modules (Ecap1/2/3/4)
57
Ecap Functional Block Diagram
58
Ecap Control and Status Registers
59
Enhanced QEP Modules (Eqep1/2)
60
Eqep Functional Block Diagram
60
Eqep Control and Status Registers
61
Enhanced Analog-To-Digital Converter (ADC) Module
62
Block Diagram of the ADC Module
63
ADC Pin Connections with Internal Reference
64
ADC Connections if the ADC Is Not Used
65
ADC Pin Connections with External Reference
65
ADC Registers
66
Enhanced Controller Area Network (Ecan) Modules (Ecan-A and Ecan-B)
67
Ecan Block Diagram and Interface Circuit
68
V Ecan Transceivers
68
Ecan-A Memory Map
69
Ecan-B Memory Map
70
CAN Register Map
71
Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)
72
SCI-A Registers
73
SCI-B Registers
73
Serial Communications Interface (SCI) Module Block Diagram
74
Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)
75
SPI-A Registers
76
SPI-B Registers
76
SPI-C Registers
77
SPI-D Registers
77
SPI Module Block Diagram (Slave Mode)
78
Inter-Integrated Circuit (I2C)
79
I2C Peripheral Module Interfaces
80
I2C-A Registers
80
Gpio Mux
81
GPIO MUX Block Diagram
81
GPIO Registers
82
F2808 GPIO MUX Table
83
Qualification Using Sampling Window
84
Device Support
85
Device and Development Support Tool Nomenclature
85
Example of Tms320X280X/2801X Device Nomenclature
86
Documentation Support
87
Tms320X280X, 2801X Peripheral Selection Guide
87
Community Resources
92
Electrical Specifications
93
Absolute Maximum Ratings
93
Recommended Operating Conditions
94
Electrical Characteristics
94
Current Consumption
95
TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-Mhz SYSCLKOUT
95
TMS320F2806 Current Consumption by Power-Supply Pins at 100-Mhz SYSCLKOUT
96
TMS320F2802, TMS320F2801 Current Consumption by Power-Supply Pins at 100-Mhz SYSCLKOUT
97
TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at 100-Mhz SYSCLKOUT
98
Reducing Current Consumption
99
Typical Current Consumption by Various Peripherals (at 100 Mhz)
99
Current Consumption Graphs
100
Typical Operational Current Versus Frequency (F2808)
100
Typical Operational Power Versus Frequency (F2808)
100
Typical Operational Current Versus Frequency (C280X)
101
Typical Operational Power Versus Frequency (C280X)
101
Emulator Connection Without Signal Buffering for the DSP
102
Timing Parameter Symbology
103
General Notes on Timing Parameters
103
Test Load Circuit
103
V Test Load Circuit
103
Device Clock Table
104
Tms320X280X Clock Table and Nomenclature (100-Mhz Devices)
104
Tms320X280X/2801X Clock Table and Nomenclature (60-Mhz Devices)
104
Clock Requirements and Characteristics
105
Input Clock Frequency
105
XCLKIN Timing Requirements - PLL Enabled
105
XCLKIN Timing Requirements - PLL Disabled
105
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
105
Power Sequencing
106
Power Management and Supervisory Circuit Solutions
106
Clock Timing
106
Power-On Reset
107
Warm Reset
108
Reset (XRS) Timing Requirements
108
General-Purpose Input/Output (GPIO)
109
GPIO - Output Timing
109
Example of Effect of Writing into PLLCR Register
109
General-Purpose Output Switching Characteristics
109
GPIO - Input Timing
110
General-Purpose Output Timing
110
Sampling Mode
110
General-Purpose Input Timing Requirements
110
Sampling Window Width for Input Signals
111
General-Purpose Input Timing
111
Low-Power Mode Wakeup Timing
112
IDLE Entry and Exit Timing
112
IDLE Mode Timing Requirements
112
IDLE Mode Switching Characteristics
112
STANDBY Entry and Exit Timing Diagram
113
STANDBY Mode Timing Requirements
113
STANDBY Mode Switching Characteristics
113
HALT Wake-Up Using Gpion
114
HALT Mode Timing Requirements
114
HALT Mode Switching Characteristics
114
Enhanced Control Peripherals
115
Enhanced Pulse Width Modulator (Epwm) Timing
115
Trip-Zone Input Timing
115
PWM Hi-Z Characteristics
115
Epwm Timing Requirements
115
Epwm Switching Characteristics
115
Trip-Zone Input Timing Requirements
115
High-Resolution PWM Characteristics at SYSCLKOUT = 60-100 Mhz
116
Enhanced Capture (Ecap) Timing Requirement
116
Ecap Switching Characteristics
116
Enhanced Quadrature Encoder Pulse (Eqep) Timing Requirements
116
Eqep Switching Characteristics
116
External Interrupt Timing
117
ADCSOCAO or ADCSOCBO Timing
117
External ADC Start-Of-Conversion Switching Characteristics
117
External Interrupt Timing Requirements
117
External Interrupt Switching Characteristics
117
I2C Electrical Specification and Timing
118
Serial Peripheral Interface (SPI) Master Mode Timing
118
I2C Timing
118
SPI Master Mode External Timing (Clock Phase = 0)
119
SPI Master Mode External Timing (Clock Phase = 0)
120
SPI Master Mode External Timing (Clock Phase = 1)
121
SPI Master Mode External Timing (Clock Phase = 1)
122
SPI Slave Mode Timing
123
SPI Slave Mode External Timing (Clock Phase = 0)
123
SPI Slave Mode External Timing (Clock Phase = 0)
124
SPI Slave Mode External Timing (Clock Phase = 1)
124
On-Chip Analog-To-Digital Converter
125
SPI Slave Mode External Timing (Clock Phase = 1)
125
ADC Electrical Characteristics (over Recommended Operating Conditions)
125
ADC Power-Up Control Bit Timing
126
ADC Power-Up Delays
126
Current Consumption for Different ADC Configurations (at 12.5-Mhz ADCCLK)
126
Definitions
127
ADC Analog Input Impedance Model
127
Sequential Sampling Mode (Single-Channel) (SMODE = 0)
128
Sequential Sampling Mode (Single-Channel) Timing
128
Sequential Sampling Mode Timing
128
Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
129
Simultaneous Sampling Mode Timing
129
Detailed Descriptions
130
Flash Timing
131
Flash Endurance for a and S Temperature Material
131
Flash Endurance for Q Temperature Material
131
Flash Parameters at 100-Mhz SYSCLKOUT
131
Flash/Otp Access Timing
132
Minimum Required Flash/Otp Wait-States at Different Frequencies
132
ROM Timing (C280X Only)
133
ROM/OTP Access Timing
133
ROM/ROM (OTP Area) Minimum Required Wait-States at Different Frequencies
133
Migrating from F280X Devices to C280X Devices
134
Migration Issues
134
Revision History
135
Mechanical Data
136
F280X Thermal Model 100-Pin GGM Results
136
F280X Thermal Model 100-Pin PZ Results
136
C280X Thermal Model 100-Pin GGM Results
136
C280X Thermal Model 100-Pin PZ Results
136
F2809 Thermal Model 100-Pin GGM Results
136
F2809 Thermal Model 100-Pin PZ Results
137
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