Emu0/1 Configuration With Additional And Gate To Meet Timing Requirements; Suggested Timings For The Emu0 And Emu1 Signals - Texas Instruments TMS320C6000 Reference Manual

Figure 10.

EMU0/1 Configuration With Additional AND Gate to Meet Timing Requirements

Backplane
XCNT_ENABLE
EMU0/1-IN
PAL
EMU0/1-OUT
To Emulator EMU0
TCK
Circuitry required for >25-ns rising/
falling edge modification
AND
To Emulator EMU1
1) The low time on EMUx−IN should be at least one TCK cycle and less than 10 ms. Software will set the EMUx−OUT
Notes:
pin to a high state.
2) To enable the open-collector driver and pullup resistor on EMU1 to provide rising/falling edges of less than 25 ns,
the modification shown in this figure is suggested. Rising edges slower than 25 ns can cause the emulator to detect
false edges during the RUNB command or when the external counter selected from the debugger analysis menu
is used.
Figure 11.

Suggested Timings for the EMU0 and EMU1 Signals

TCK
EMU0/1-OUT
EMU0/1-IN
SPRU641
Open
Collector
Drivers
Pullup
Resistor
Open
Collector
Drivers
EMU1
Up to
m boards
EMU1 signal from other boards
Emulation Design Considerations
Target Board 1
Pullup Resistor
EMU0/1
Device Device
. . .
1 n
Target Board m
Pullup Resistor
EMU0/1
Device
Device
. . .
1 n
Designing for JTAG Emulation 23