Data Bus Topology; Figure 23. Data Signal Routing Topology; Table 20. Intel 852Gme Chipset Gmch/Mch Memory Data Signal Group Routing - Intel 852GME Design Manual

R
6.3.2.1.

Data Bus Topology

Figure 23. Data Signal Routing Topology

GMCH
GM CH
Die
The data signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within the
DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non-DDR
related signals. Data signals should be routed on inner layers with minimized external trace lengths.
Table 20. Intel 852GME Chipset GMCH/MCH Memory Data Signal Group Routing Guidelines
Signal Group
Motherboard Topology
Reference Plane
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Minimum Spacing to Trace Width Ratio
Minimum Isolation Spacing to non-DDR Signals
Package Length P1
Trace Length L1 – GMCH/MCH Signal Ball to Series
Termination Resistor Pad
Trace Length L2 – Series Termination Resistor Pad to
First SO-DIMM Via
Stub Length S0, S1 – Stub from Via to SO-DIMM Pad
Total Length L1 + L2 + S0 – Total Length from
GMCH/MCH to First SO-DIMM Pad
Total Length L1 + L2 + L3 + S1 – Total Length from
GMCH/MCH to Second SO-DIMM Pad
Total Length S0 + L3 + S1– Total SO-DIMM pad to SO-
DIMM pad spacing
74
L1
P1
SO-DIMM0 PAD
Parameter
® ®
Intel 852GME, Intel 852GMV and Intel
System Memory Design Guidelines (DDR-SDRAM)
Rs
L2 L3
S0
SDQ[71:0], SDQS[8:0], SDM[8:0]
Daisy Chain with Parallel Termination
Ground Referenced
55 +/- 15%
Inner layers: 4 mils
Outer layers: 5 mils
SDQ/SDM: 2 to 1 (e.g. 8 mil space to 4 mil trace)
SDQS: 3 to 1 (e.g. 12 mil space to 4 mil trace)
20 mils
700 mils +/- 300 mils (See Table 22 for details)
Min = 0.5"
Max = 3.75"
Max = 0.75"
Max = 0.25"
Min = 0.5"
Max = 4.0"
Min = 0.75"
Max = 4.5"
Min = 0.25"
Max = 1.0"
®
852PM Chipset Platforms Design Guide
Vtt
Rt
L4
S1
SO-DIMM1 PAD
Definition