Data Bus Topology; Figure 36. Data Signal Routing Topology - Intel 855GM Design Manual

System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration
To facilitate routing, swapping of the byte lanes is allowed for SDQ[63:0] only. Bit swapping within the
byte lane is also allowed for SDQ[63:0] only. The check bits, SDQ[71:64], cannot be byte lane swapped
with another SDQ byte lane. Also, bit swapping within the SDQ[71:64] byte lane is not allowed. It is
suggested that the parallel termination be placed on both sides of SO-DIMM1 to simplify routing and
minimize trace lengths. All internal and external signals should be ground referenced to keep the path of
the return current continuous.
Resistor packs are acceptable for the series (Rs) and parallel (Rt) data and strobe termination resistors,
but data and strobe signals can't be placed within the same R pack as the command or control signals.
The table and diagrams below depict the recommended topology and layout routing guidelines for the
DDR-SDRAM data signals.
Intel recommends that the full data bus SDQ[71:0], mask bus SDM[8:0], and strobe signals SDQS[8:0]
be routed on the same internal signal layer. It is required that the SDQ byte group and the associated
SDM and SDQS signals within a byte lane be routed on the same internal layer.
The total length of SDQ, SDM, and SDQS traces between the GMCH and the SO-DIMMs must be
within the range defined in the overall guidelines, and is also constrained by a length range boundary
based on SCK/SCK# clock length, and a SDQ/SDM to SDQS length matching requirement within each
byte lane. Note also that all length matching must be done inclusive of package length. A table of SDQ,
SDM, and SDQS package lengths is provided at the end of this Section to facilitate this process.
There are two levels of matching implemented on the data bus signals.
• The first is the length range constraint on the SDQS signals based on clock reference length.
• The second is SDQ/SDM to SDQS length matching within a byte lane.
The length of the SDQS signal for each byte lane must fall within a range determined by the clock
reference length, as defined in the SDQS to SCK/SCK length matching Section. The actual length of
SDQS for each byte lane may fall anywhere within this range based on placement and routing flow.
Once the SDQS length for a byte lane is established, the SDQ and SDM signals within the byte lane
must be length matched to each other, inclusive of package length, as described in the SDQ to SDQS
length matching Section 6.3.4.3.
6.3.4.1.

Data Bus Topology

Figure 36. Data Signal Routing Topology

GMCH
GM CH
Die
The data signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within the
DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non-DDR
related signals. Data signals should be routed on inner layers with minimized external trace lengths.
84
Rs
L1
P1
SO-DIMM0 PAD
L2 L3
S0 S1
®
Intel 855GM/855GME Chipset Platform Design Guide
R
Vtt
Rt
L4
SO-DIMM1 PAD