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5.1.3.
Data Bus Error Checking Policy
The Pentium II data bus error checking can be enabled or disabled. After active RESET#,
data bus error checking is always disabled. Data bus error checking can be enabled under
software control.
5.1.4.
Response Signal Parity Error Checking Policy
The Pentium II processor system bus supports parity protection for the response signals,
RS[2:0]#. The parity checking on these signals can be enabled or disabled. After active
RESET#, response signal parity checking is disabled. It can be enabled under software
control.
5.1.5.
AERR# Driving Policy
The Pentium II address bus parity protection on the Request signals, A[35:3]#, ADS# and
REQ[4:0]#. However, driving the address parity results on the AERR# pin is optional. After
active RESET#, address bus parity error driving is always disabled. It may be enabled under
software control.
5.1.6.
AERR# Observation Policy
The AERR# input receiver is enabled if A8# is observed active on active-to-inactive
transition of RESET#. No software control is available to perform this function.
5.1.7.
BERR# Driving Policy for Initiator Bus Errors
A Pentium II processor system bus agent can be enabled to drive the BERR# signal if it
detects a bus error. After active RESET#, BERR# signal driving is disabled for detected
errors. It may be enabled under software control.
5.1.8.
BERR# Driving Policy for Target Bus Errors
A Pentium II processor system bus agent can be enabled to drive the BERR# signal if the
addressed (target) bus agent detects an error. After active RESET#, BERR# signal driving is
disabled on target bus errors. It may be enabled under software control. The processor does
not drive BERR# on target detected bus errors.
CONFIGURATION
5-3
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