Table of Contents
Advertisement
Principles of Operation
iSBC 432/100
23
20 19
16 15
12 11
8 7
4 3
24-BIT PROCESSOR
- - - - - - - - - - - . . . . - - - - - - - PHYSICAL ADDRESS
OFFSET
REGISTER
4 3
0
__
__..
__
...
FULL
ADDER _ _ _ _ _ _ _.
20-BIT MULTIBUS
_ _ _ _ _ _ _ _ ...._ _ _ _ _ _ ADDRESS
Figure 4-4. 24-Bit Processor Physical Address to 20-Bit Multibus™ Address Conversion
171820-19
3.
The remammg eight bits are added to an
address offset contained in an 8-bit offset
register. The result of this calculation is
loaded into two additional 4-bit counters.
The offset register (an 8-bit 1/0 port on the
board) may be loaded by a Multibus master
as discussed in paragraph 4.18.
Once this initial address has been computed and
latched into the five address counters, the data
transfer state machine controls the actual data
transfers between the bus and the GDP. As each 8- or
16-bit transfer is completed, the state machine
updates (increments) the 20-bit address (stored in the
counters) in order to correctly cycle through
multibyte transfer requests.
4.6 DAT A TRANSFER ST A TE MACHINE
The data tr an sf er state machine is composed of a
programmable logic array (PLA), a state register, a
transfer counter, _and a command decoder. The PLA,
which is the heart of the state machine, generates the
signals required to synchronize Multibus operations
with processor data transfers. The state machine
operates in either an 8-bit or 16-bit Multibus mode. A
jumper option may be strapped by the user to force
all operations to be performed in the 8-bit mode.
Otherwise, in the 16-bit mode, all single byte
transfers and all multibyte transfers initiated on odd
addresses are forced into the 8-bit mode. The follow-
ing descriptions of data transfer operations are
graphically depicted in figure 4-5.
In the 8-bit mode, all Multibus operations are 8-bit
(byte) transfers. If a single-byte read is requested by
the processor, this byte is transferred from the least
significant eight Multibus data lines (DATO/-
DA T7 /) through a transparent latch (A54) to the
4-4
least significant byte of the ACD bus (ACDO-ACD7)
as illustrated in figure 4-5a. When more than one
byte is requested, two 8-bit Multibus operations are
combined into a single 16-bit processor transfer. The
first Multibus read latches DATO/-DAT7/ into
transparent latch A54, driving ACDO-ACD7. After
incrementing the memory address,
the second
Multibus read operation transfers data from DATO/-
DAT7 I onto ACD8-ACDF (through transceiver
A52). A double-byte read transfer is illustrated in
figure 4-Sb.
During a single-byte write transfer, data on ACDO-
ACD7 is transferred to the DATO/-DAT7/ data lines
of the Multibus bus through transceiver A53 (refer to
figure 4-Sc). Multiple data byte transfers perform
two Multibus write operations for each 16-bit ACD
bus transfer. The first . Multibus write transfers
ACDO-ACD7 to the DATO/-DAT7/ data lines
(through transceiver A53). After incrementing the
memory address, the second Multibus write opera-
tion transfers ACD8-ACDF to the DATO/-DAT7/
Multibus data lines. This double-byte write transfer
is shown in figure 4-5d.
In the 16-bit mode, a single byte read is performed
through A54 (if the address is odd) or through A53
(if the address is even). A single-byte write transfers
data through transceiver A53. In both a single-byte
write and a single-byte read transfer, ACDO-ACD7
are connected to Multibus data lines DATO/-DAT7/
(figure 4-Se to 4-5g). Multibyte transfers in the 16-bit
mode are performed as a sequence of double-byte
Multibus/processor operations. Each double-byte
read transfers 16 bits of data from the multibus bus
to the ACD bus by means of A53 (least significant
byte) and A5 l (most significant byte). Multibyte
write operations utilize the same data path as used by
the multibyte read transfers, but in the opposite
direction. Multibyte transfers in the 16-bit mode are
illustrated in figure 4-Sh.
Advertisement
Table of Contents
