Client Management; Wrpciconfiglocal() Memory Controller And Iio Device/Function Support; Peci Client Response During Power-Up - Intel Xeon Processor E5-1600 Datasheet

2.5.2.10.3 WrPCIConfigLocal() Capabilities
On the processor PECI clients, the PECI WrPCIConfigLocal() command provides a
method for programming certain integrated memory controller and IIO functions as
described in
Datasheet Volume Two for more details on specific register definitions. It also enables
writing to processor REUT (Robust Electrical Unified Test) registers associated with the
Intel QPI, PCIe* and DDR3 functions.
Table 2-15. WrPCIConfigLocal() Memory Controller and IIO Device/Function Support
Bus Device
0000 0-5
0001 15
0001 15
0001 15
0001 16
0001 16
2.5.3

Client Management

2.5.3.1 Power-up Sequencing
The PECI client will not be available when the PWRGOOD signal is de-asserted. Any
transactions on the bus during this time will be completely ignored, and the host will
read the response from the client as all zeroes. PECI client initialization is completed
approximately 100 µS after the PWRGOOD assertion. This is represented by the start of
the PECI Client "Data Not Ready" (DNR) phase in
PECI client will respond normally to the Ping() and GetDIB() commands and return the
highest processor die temperature of 0x0000 to the GetTemp() command. All other
commands will get a 'Response Timeout' completion in the DNR phase as shown in
Table 2-16. All PECI services with the exception of core MSR space accesses become
available ~500 µS after RESET_N de-assertion as shown in
fully functional with all services including core accesses being available when the core
comes out of reset upon completion of the RESET microcode execution.
In the event of the occurrence of a fatal or catastrophic error, all PECI services with the
exception of core MSR space accesses will be available during the DNR phase to
facilitate debug through configuration space accesses.
Table 2-16. PECI Client Response During Power-Up (Sheet 1 of 2)
Command
Ping()
GetDIB()
GetTemp()
RdPkgConfig()
WrPkgConfig()
RdIAMSR()
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
Table 2-15. Refer to the Intel® Xeon® Processor E5 Product Family
Function Offset Range
0-7 000-FFFh
0 104h-127h
0 180h-1AFh
1 080h-0CFh
0, 1, 4, 5 104h-18Bh
1F4h-1FFh
2, 3, 6, 7 104h-147h
Response During
'Data Not Ready'
Fully functional
Fully functional
Client responds with a 'hot' reading or 0x0000
Client responds with a timeout completion
code of 0x81
Client responds with a timeout completion
code of 0x81
Client responds with a timeout completion
code of 0x81
Description
Integrated I/O (IIO) Configuration Registers
Integrated Memory Controller MemHot Registers
Integrated Memory Controller SMBus Registers
Integrated Memory Controller RAS Registers (Scrub/Spare)
Integrated Memory Controller Thermal Control Registers
Integrated Memory Controller Error Registers
Figure 2-49. While in this phase, the
Figure
'Available Except Core Services'
Fully functional
Fully functional
Fully functional
Fully functional
Fully functional
Client responds with a timeout
completion code of 0x81
2-49. PECI will be
Response During
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