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Table 60.
Case 1, USB Routing Guidelines – EP80579 to Connector (Sheet 2 of 2)
Length Tuning Requirements
EP80579 Breakout
Note:
1.
Strictly observe the characteristic trace impedance. In this regard, requirements for the layers, trace
width, and trace spacing are secondary.
Figure 109. USB Trace Lengths From Controller to Connector
EP80579
Table 61.
Case 2, USB Routing Guidelines – EP80579 Front Panel Option (Sheet 1 of 2)
Signal Group
Reference Plane
Layer Assignment
Characteristic Trace Impedance
1
(Zo)
Nominal Trace Width
Nominal Trace Spacing
Nominal Trace Length
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
166
®
Intel
EP80579 Integrated Processor Product Line—Universal Serial Bus (USB) Interface
Parameter
Length matching over LT within a pair is 60 mils or
less.
4 mils width with 4 mils spacing for maximum of
500 mils, minimize this length.
L1
L1'
Parameter
USBp[1:0], USBn[1:0]
Ground Referenced, Stripline or Microstrip
Layers 3 or 8
Trace Spacing, edge-to-edge:
Pair-to-pair spacing, edge to edge: 45 mils minimum
Spacing to clock signals: 45 mils minimum
Spacing to non-clock signals: 45 mils minimum
Keep all lengths as short as possible.
L1 = 1500 mils maximum
L2 = LT - L1 - L3
L3 = 1000 mils maximum
LT (to connector =
2
LT to a header is dependent on the length of the cable
connecting the header to the front panel daughter
card. See
requirements.
Routing Guidelines
LT = L1 + L2
Choke
Routing Guidelines
90 Ω ±10% (differential)
4.75 mils – microstrip
4.5 mils – stripline
5.25 mils–microstrip
5.5 mils– stripline
2–11 in. – microstrip (differential)
2–10 in. – stripline (differential)
Table 63
for detailed trace length
Figure
-
-
L2
USB
Connector
L2'
Figure
-
-
-
-
Figure 112
Figure 113
Figure 112
Figure 113
Figure 110
May 2010
Order Number: 320068-005US
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