Vc0Rsts-Vc0 Resource Status Register; Peg_Tc-Pci Express Completion Time-Out Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.7.6 VC0RSTS—VC0 Resource Status Register
This register reports the Virtual Channel specific status.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
15:2
1
0:0
2.7.7 PEG_TC—PCI Express Completion Time-out Register
This register reports PCI Express configuration control of PCI Express Completion Time-
out related parameters that are not required by the PCI Express specification.
B/D/F/Type:
Address Offset:
Access:
Bit
31:15
14:12
11:0
Datasheet, Volume 2
0/1/0–2/MMR
11A–11Bh
0002h
RO-V
16 bits
0000h
Reset RST/
Attr
Value PWR
RO 0h
RO-V 1b Uncore
RO 0h
0/1/0–2/MMR
208–20Bhh
RW
Reset RST/
Attr
Value PWR
00000000
RO 00000000
0b
RW 111b
00000000
RO
0000b
Description
Reserved
VC0 Negotiation Pending (VC0NP)
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation
(initialization or disabling).
This bit indicates the status of the process of Flow Control
initialization. It is set by default on Reset, as well as whenever the
corresponding Virtual Channel is Disabled or the Link is in the
DL_Down state. It is cleared when the link successfully exits the
FC_INIT2 state.
Before using a Virtual Channel, software must check whether the
VC Negotiation Pending fields for that Virtual Channel are cleared
in both Components on a Link.
Reserved
Description
Reserved
PCI Express Completion Time-out (PEG_TC)
This register determines the number of milliseconds the
Transaction Layer will wait to receive an expected completion. To
avoid hang conditions, the Transaction Layer will generate a
dummy completion to the requestor if it does not receive the
completion within this time period.
000 = Disable
001 = Reserved
010 = Reserved
100 = Reserved
101 = Reserved
110 = Reserved
x11 = 48 ms – for normal operation
Reserved
127