Peak Bandwidth Summary; System Configurations - Intel Pentium M Processor Design Manual

— PCI-PCI Bridge Architecture Specification, Revision 1.1, compliant
— PCI Hot-Plug Specification, Revision 1.1, compliant
— One PCI Hot-Plug Controller (PHPC) per PCI/PCI-X interface
— One IOxAPIC per PCI/PCI-X Interface (16 external, eight internal interrupts)
— SMBus target for access to all internal PCI registers
1.3.4

Peak Bandwidth Summary

Table 3 describes the clock maximum speed, sample rate, and peak bandwidth for each of the
interfaces in the Intel
®
Table 3. Intel Pentium
Summary
Interface
System Bus (Data)
DDR Interface
• Dual Channel
• Single Channel
Hub Interface A
Hub Interface B, C, D
PCI-X
1.3.5

System Configurations

Figure 1 illustrates an example Intel
embedded platforms using the Intel
Design Guide
® ®
Intel Pentium M Processor and Intel
®
E7501 Chipset-based platform.
®
M Processor or Intel
Clock Speed
(MHz)
100
100
66
66
133
®
E7501 Chipset-based system configuration for server or
®
Pentium
®
®
E7501 Chipset Platform Peak Bandwidth
Samples per Data Width
Clock (Bytes)
4 8
2 16
4 1
8 2
1 8
®
M Processor.
E7501 Chipset Platform
Introduction
Bandwidth
(Mbytes/s)
3200
3200 (Dual Channel)
2200 (Single Channel)
266
1066
1066
29