Microchip Technology dsPIC33EP GP50 Series Manual

Microchip Technology dsPIC33EP GP50 Series Manual

16-bit microcontrollers and digital signal controllers with high-speed pwm, op amps and advanced analog

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16-Bit Microcontrollers and Digital Signal Controllers
with High-Speed PWM, Op Amps and Advanced Analog
Operating Conditions
• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS
• 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS
• 3.0V to 3.6V, -40°C to +150°C, DC to 40 MIPS
Core: 16-Bit dsPIC33E/PIC24E CPU
• Code Efficient (C and Assembly) Architecture
• Two 40-Bit Wide Accumulators
• Single Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle, Mixed-Sign MUL plus Hardware Divide
• 32-Bit Multiply Support
Clock Management
• 1.0% Internal Oscillator
• Programmable PLLs and Oscillator Clock Sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer (WDT)
• Fast Wake-up and Start-up
Power Management
• Low-Power Management modes (Sleep, Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
• 0.6 mA/MHz Dynamic Current (typical)
• 30 µA I
Current (typical)
PD
High-Speed PWM
• Up to Three PWM Pairs with Independent Timing
• Dead Time for Rising and Falling Edges
• 7.14 ns PWM Resolution
• PWM Support for:
- DC/DC, AC/DC, Inverters, PFC, Lighting
- BLDC, PMSM, ACIM, SRM
• Programmable Fault Inputs
• Flexible Trigger Configurations for ADC Conversions
Advanced Analog Features
• ADC module:
- Configurable as 10-bit, 1.1 Msps with four S&H or
12-bit, 500 ksps with one S&H
- Six analog inputs on 28-pin devices and up to
16 analog inputs on 64-pin devices
• Flexible and Independent ADC Trigger Sources
• Up to Three Op Amp/Comparators with
Direct Connection to the ADC module:
- Additional dedicated comparator
- Programmable references with 32 voltage points
• Charge Time Measurement Unit (CTMU):
®
- Supports mTouch
capacitive touch sensing
- Provides high-resolution time measurement (1 ns)
- On-chip temperature measurement
 2011-2020 Microchip Technology Inc.
dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X
Timers/Output Compare/Input Capture
• 12 General Purpose Timers:
- Five 16-bit and up to two 32-bit timers/counters
- Four Output Compare (OC) modules, configurable
as timers/counters
- PTG module with two configurable timers/counters
- 32-bit Quadrature Encoder Interface (QEI) module,
configurable as a timer/counter
• Four Input Capture (IC) modules
• Peripheral Pin Select (PPS) to allow Function Remap
• Peripheral Trigger Generator (PTG) for Scheduling
Complex Sequences
Communication Interfaces
• Two UART modules (17.5 Mbps):
- With support for LIN/J2602 protocols and IrDA
• Two Four-Wire SPI modules (15 Mbps)
• ECAN™ module (1 Mbaud) CAN 2.0B Support
2
• Two I
C modules (up to 1 Mbaud) with SMBus Support
• PPS to allow Function Remap
• Programmable Cyclic Redundancy Check (CRC)
Direct Memory Access (DMA)
• 4-Channel DMA with User-Selectable Priority Arbitration
• UART, SPI, ADC, ECAN, IC, OC and Timers
Input/Output
• Sink/Source 12 mA or 6 mA, Pin-Specific for
Standard V
/V
OH
for Non-Standard V
• 5V Tolerant Pins
• Peripheral Pin Select (PPS) to allow Digital Function
Remapping
• Selectable Open-Drain, Pull-ups and Pull-Downs
• Up to 5 mA Overvoltage Clamp Current
• Change Notification Interrupts on All I/O Pins
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1, -40°C to +125°C)
• AEC-Q100 REVG (Grade 0, -40°C to +150°C)
• Class B Safety Library, IEC 60730
Debugger Development Support
• In-Circuit and In-Application Programming
• Two Program and Two Complex Data Breakpoints
• IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Trace and Run-Time Watch
, Up to 22 or 14 mA, respectively
OL
1
OH
DS70000657J-page 1
®

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Summary of Contents for Microchip Technology dsPIC33EP GP50 Series

  • Page 1 • IEEE 1149.2 Compatible (JTAG) Boundary Scan • Charge Time Measurement Unit (CTMU): • Trace and Run-Time Watch ® - Supports mTouch capacitive touch sensing - Provides high-resolution time measurement (1 ns) - On-chip temperature measurement  2011-2020 Microchip Technology Inc. DS70000657J-page 1...
  • Page 2 On 28-pin devices, Comparator 4 does not have external connections. Refer to Section 25.0 “Op Amp/Comparator Module” for details. Only SPI2 is remappable. INT0 is not remappable. The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory.  2011-2020 Microchip Technology Inc. DS70000657J-page 2...
  • Page 3 Section 25.0 “Op Amp/Comparator Module” for details. Only SPI2 is remappable. INT0 is not remappable. Only the PWM Faults are remappable. The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory.  2011-2020 Microchip Technology Inc. DS70000657J-page 3...
  • Page 4 Section 25.0 “Op Amp/Comparator Module” for details. Only SPI2 is remappable. INT0 is not remappable. Only the PWM Faults are remappable. The SSOP and VTLA packages are not available for devices with 512 Kbytes of memory.  2011-2020 Microchip Technology Inc. DS70000657J-page 4...
  • Page 5 Section 11.0 “I/O Ports” for more information. 3: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 5...
  • Page 6 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 6...
  • Page 7 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 7...
  • Page 8 3: If the op amp is selected when OPMODE (CMxCON[10]) = 1, the OAx input is used; otherwise, the ANx input is used. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 8...
  • Page 9 3: If the op amp is selected when OPMODE (CMxCON[10]) = 1, the OAx input is used; otherwise, the ANx input is used. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 9...
  • Page 10 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 10...
  • Page 11 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 11...
  • Page 12 Section 11.0 “I/O Ports” for more information. 3: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 12...
  • Page 13 Section 11.0 “I/O Ports” for more information. 3: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 13...
  • Page 14 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 14...
  • Page 15 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 15...
  • Page 16 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 16...
  • Page 17 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 17...
  • Page 18 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 18...
  • Page 19 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 19...
  • Page 20 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 20...
  • Page 21 3: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to externally. 4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 21...
  • Page 22 4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to externally. 5: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 22...
  • Page 23 4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to externally. 5: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 23...
  • Page 24: Table Of Contents

    32.0 DC and AC Device Characteristics Graphs..........................481 33.0 Packaging Information................................485 Appendix A: Revision History................................521 Index ......................................... 533 The Microchip Website..................................541 Customer Change Notification Service .............................. 541 Customer Support ....................................541 Product Identification System................................543  2011-2020 Microchip Technology Inc. DS70000657J-page 24...
  • Page 25 When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products.  2011-2020 Microchip Technology Inc. DS70000657J-page 25...
  • Page 26 • “Programming and Diagnostics” (www.microchip.com/DS70608) • “Op Amp/Comparator” (www.microchip.com/DS70000357) • “Programmable Cyclic Redundancy Check (CRC)” (www.microchip.com/DS70346) • “Device Configuration” (www.microchip.com/DS70000618) • “Peripheral Trigger Generator (PTG)” (www.microchip.com/DS70000669) • “Charge Time Measurement Unit (CTMU)” (www.microchip.com/DS70661)  2011-2020 Microchip Technology Inc. DS70000657J-page 26...
  • Page 27: Device Overview

    SPI1, UART1, QEI1 CTMU Timers SPI2 UART2 Peripheral Modules Note 1: This feature or peripheral is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. This feature or peripheral is only available on dsPIC33EPXXXGP/MC50X devices.  2011-2020 Microchip Technology Inc. DS70000657J-page 27...
  • Page 28 Not all pins are available in all package variants. See the “Pin Diagrams” section for pin availability. There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 28...
  • Page 29 Not all pins are available in all package variants. See the “Pin Diagrams” section for pin availability. There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 29...
  • Page 30 Not all pins are available in all package variants. See the “Pin Diagrams” section for pin availability. There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in Table 27-2.  2011-2020 Microchip Technology Inc. DS70000657J-page 30...
  • Page 31: Guidelines For Getting Started With 16-Bit Digital Signal Controllers And Microcontrollers

    Additionally, the following pins may be required: • V - pins are used when external voltage reference for the ADC module is implemented Note: The AV and AV pins must be connected, independent of the ADC voltage reference source.  2011-2020 Microchip Technology Inc. DS70000657J-page 31...
  • Page 32 2: R1  470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin and V specifications are met.  2011-2020 Microchip Technology Inc. DS70000657J-page 32...
  • Page 33 ICD 3” (poster) DS51765 Guard Trace ® • “MPLAB ICD 3 Design Advisory” DS51764 ® • “MPLAB REAL ICE™ In-Circuit Emulator User’s Oscillator Pins Guide” DS51616 ® • “Using MPLAB REAL ICE™ In-Circuit Emulator” (poster) DS51749  2011-2020 Microchip Technology Inc. DS70000657J-page 33...
  • Page 34 Alternatively, connect a 1k to 10k resistor between V Figure 2-4 through Figure 2-8. and unused pins, and drive the output to logic low. FIGURE 2-4: BOOST CONVERTER IMPLEMENTATION INPUT OUTPUT Driver ADC Channel Op Amp/ ADC Channel Comparator Output dsPIC33EP  2011-2020 Microchip Technology Inc. DS70000657J-page 34...
  • Page 35 12V Input 5V Output Driver Op Amp/ Channel Comparator Channel dsPIC33EP FIGURE 2-6: MULTIPHASE SYNCHRONOUS BUCK CONVERTER 3.3V Output 12V Input Driver Driver Channel Driver Op Amp/Comparator dsPIC33EP Op Amp/Comparator Op Amp/Comparator ADC Channel  2011-2020 Microchip Technology Inc. DS70000657J-page 35...
  • Page 36 Channel Comparator dsPIC33EP ADC Channel FIGURE 2-8: BEMF VOLTAGE MEASURED USING THE ADC MODULE dsPIC33EP/PIC24EP BLDC PWM3H PWM3L 3-Phase PWM2H PWM2L Inverter PWM1H PWM1L R34 R36 Fault FLTx Demand Phase Terminal Voltage Feedback  2011-2020 Microchip Technology Inc. DS70000657J-page 36...
  • Page 37: Cpu

    The instruction set includes many addressing modes addressing mode group, depending upon its functional and was designed for optimum C compiler efficiency. requirements. As many as six addressing modes are supported for each instruction.  2011-2020 Microchip Technology Inc. DS70000657J-page 37...
  • Page 38 W Register Array Divide Support Engine 16-Bit ALU Instruction Control Signals Decode and to Various Blocks Control Power, Reset Ports and Oscillator Modules Peripheral Modules Note 1: This feature is not available on PIC24EPXXXGP/MC20X devices.  2011-2020 Microchip Technology Inc. DS70000657J-page 38...
  • Page 39 DO Loop End Address Register (High and Low) CORCON Contains DSP Engine, DO Loop Control and Trap Status bits Note 1: This register is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. The DOSTARTH and DOSTARTL registers are read-only.  2011-2020 Microchip Technology Inc. DS70000657J-page 39...
  • Page 40 DO Loop Start Address and Stack DOEND DO Loop End Address and Stack CORCON CPU Core Control Register IPL2 IPL1 IPL0 STATUS Register Note 1: This feature or bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.  2011-2020 Microchip Technology Inc. DS70000657J-page 40...
  • Page 41 In the event you are not able to access the product page using the link above, enter • All related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en555464  2011-2020 Microchip Technology Inc. DS70000657J-page 41...
  • Page 42 A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not be modified using bit operations.  2011-2020 Microchip Technology Inc. DS70000657J-page 42...
  • Page 43 A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not be modified using bit operations.  2011-2020 Microchip Technology Inc. DS70000657J-page 43...
  • Page 44 This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. This bit is always read as ‘0’. The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level.  2011-2020 Microchip Technology Inc. DS70000657J-page 44...
  • Page 45 This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only. This bit is always read as ‘0’. The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level.  2011-2020 Microchip Technology Inc. DS70000657J-page 45...
  • Page 46 (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.  2011-2020 Microchip Technology Inc. DS70000657J-page 46...
  • Page 47: Memory Organization

    (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0x800FF6 0x800FF8 USERID 0x800FFE 0x801000 Reserved 0xF9FFFE 0xFA0000 Write Latches 0xFA0002 0xFA0004 Reserved 0xFEFFFE 0xFF0000 DEVID 0xFF0002 0xFF0004 Reserved 0xFFFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 47...
  • Page 48 (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0x800FF6 0x800FF8 USERID 0x800FFE 0x801000 Reserved 0xF9FFFE 0xFA0000 Write Latches 0xFA0002 0xFA0004 Reserved 0xFEFFFE 0xFF0000 DEVID 0xFF0002 0xFF0004 Reserved 0xFFFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 48...
  • Page 49 (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0x800FF6 0x800FF8 USERID 0x800FFE 0x801000 Reserved 0xF9FFFE 0xFA0000 Write Latches 0xFA0002 0xFA0004 Reserved 0xFEFFFE 0xFF0000 DEVID 0xFF0002 0xFF0004 Reserved 0xFFFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 49...
  • Page 50 (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0x800FF6 0x800FF8 USERID 0x800FFE 0x801000 Reserved 0xF9FFFE 0xFA0000 Write Latches 0xFA0002 0xFA0004 Reserved 0xFEFFFE 0xFF0000 DEVID 0xFF0002 0xFF0004 Reserved 0xFFFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 50...
  • Page 51 (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0x800FF6 0x800FF8 USERID 0x800FFE 0x801000 Reserved 0xF9FFFE 0xFA0000 Write Latches 0xFA0002 0xFA0004 Reserved 0xFEFFFE 0xFF0000 DEVID 0xFF0002 0xFF0004 Reserved 0xFFFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 51...
  • Page 52 PROGRAM MEMORY ORGANIZATION least significant word most significant word PC Address Address (lsw Address) 0x000001 0x000000 00000000 0x000003 0x000002 00000000 0x000005 00000000 0x000004 0x000007 00000000 0x000006 Program Memory Instruction Width ‘Phantom’ Byte (read as ‘0’)  2011-2020 Microchip Technology Inc. DS70000657J-page 52...
  • Page 53 (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address.  2011-2020 Microchip Technology Inc. DS70000657J-page 53...
  • Page 54 SRAM Space Y Data RAM (Y) 0x1FFF 0x1FFE 0x2001 0x2000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory Space (PSV) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 54...
  • Page 55 SRAM Space 0x2000 Y Data RAM (Y) 0x2FFF 0x2FFE 0x3001 0x3000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory Space (PSV) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 55...
  • Page 56 SRAM Space Y Data RAM (Y) 0x4FFF 0x4FFE 0x5001 0x5000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory Space (PSV) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 56...
  • Page 57 0x7FFF 0x7FFE Y Data RAM (Y) 0x8001 0x8000 0x8FFF 0x8FFE 0x9001 0x9000 Optionally Mapped into Program Memory Space X Data (PSV) Unimplemented (X) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 57...
  • Page 58 0x8FFF 0x8FFE 0x9001 0x9000 Y Data RAM (Y) 0xCFFF 0xCFFE 0xD001 0xD000 Optionally Mapped into Program Memory Space (PSV) X Data Unimplemented (X) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 58...
  • Page 59 X Data RAM (X) SRAM Space 0x1FFF 0x1FFE 0x2001 0x2000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory Space (PSV) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 59...
  • Page 60 0x1FFF 0x1FFE SRAM Space 0x2001 0x2000 0x2FFF 0x2FFE 0x3001 0x3000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory Space (PSV) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 60...
  • Page 61 X Data RAM (X) 0x2001 0x2000 16-Kbyte SRAM Space 0x4FFF 0x4FFE 0x5001 0x5000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory Space (PSV) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 61...
  • Page 62 0x2000 32-Kbyte SRAM Space 0x7FFF 0x7FFE 0x8001 0x8000 0x8FFF 0x8FFE 0x9001 0x9000 Optionally Mapped into Program Memory Space (PSV) X Data Unimplemented (X) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 62...
  • Page 63 0x2000 48-Kbyte SRAM Space 0x7FFF 0x7FFE 0x8001 0x8000 0xCFFF 0xCFFE 0xD001 0xD000 Optionally Mapped into Program Memory Space (PSV) X Data Unimplemented (X) 0xFFFF 0xFFFE Note: Memory areas are not shown to scale.  2011-2020 Microchip Technology Inc. DS70000657J-page 63...
  • Page 64 All data memory writes, including in DSP instructions, view Data Space as combined X and Y address space. The boundary between the X and Y Data Spaces is device-dependent and is not user-programmable.  2011-2020 Microchip Technology Inc. DS70000657J-page 64...
  • Page 65 Special Function Register Maps TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND dsPIC33EPXXXGP50X DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
  • Page 66 TABLE 4-1: CPU CORE REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND dsPIC33EPXXXGP50X DEVICES ONLY (CONTINUED) File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
  • Page 67 TABLE 4-2: CPU CORE REGISTER MAP FOR PIC24EPXXXGP/MC20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 68 TABLE 4-3: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 69 TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 70 TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY (CONTINUED) File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 71 TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 72 TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY (CONTINUED) File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 73 TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 74 TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY (CONTINUED) File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 75 TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 76 TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXMC50X DEVICES ONLY (CONTINUED) File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 77 TABLE 4-8: TIMER1 THROUGH TIMER5 REGISTER MAP Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets TMR1...
  • Page 78 TABLE 4-9: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 4 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
  • Page 79 TABLE 4-10: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 4 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
  • Page 80 TABLE 4-11: PTG REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets PTGCST 0AC0 PTGEN...
  • Page 81 TABLE 4-12: PWM REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
  • Page 82 TABLE 4-14: PWM GENERATOR 2 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
  • Page 83 TABLE 4-16: QEI1 REGISTER MAP FOR dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
  • Page 84 TABLE 4-17: I2C1 AND I2C2 REGISTER MAP File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets I2C1RCV...
  • Page 85 TABLE 4-19: SPI1 AND SPI2 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets SPI1STAT...
  • Page 86 TABLE 4-20: ADC1 REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets ADC1BUF0 0300...
  • Page 87 TABLE 4-21: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1[0]) = 0 OR 1 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
  • Page 88 TABLE 4-23: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1[0]) = 1 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
  • Page 89 TABLE 4-23: ECAN1 REGISTER MAP WHEN WIN (C1CTRL1[0]) = 1 FOR dsPIC33EPXXXMC/GP50X DEVICES ONLY (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
  • Page 90 TABLE 4-24: CRC REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets CRCCON1 0640...
  • Page 91 TABLE 4-27: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGP/MC204/504 AND PIC24EPXXXGP/MC204 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
  • Page 92 TABLE 4-29: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR PIC24EPXXXMC20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
  • Page 93 TABLE 4-31: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
  • Page 94 TABLE 4-33: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
  • Page 95 TABLE 4-34: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets NVMCON 0728...
  • Page 96 TABLE 4-37: PMD REGISTER MAP FOR PIC24EPXXXGP20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets...
  • Page 97 TABLE 4-39: PMD REGISTER MAP FOR dsPIC33EPXXXGP50X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets...
  • Page 98 TABLE 4-41: PMD REGISTER MAP FOR dsPIC33EPXXXMC20X DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets...
  • Page 99 TABLE 4-42: OP AMP/COMPARATOR REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets CMSTAT 0A80...
  • Page 100 TABLE 4-45: DMAC REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets DMA0CON 0B00...
  • Page 101 TABLE 4-46: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 102 TABLE 4-49: PORTD REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 103 TABLE 4-52: PORTG REGISTER MAP FOR PIC24EPXXXGP/MC206 AND dsPIC33EPXXXGP/MC206/506 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 104 TABLE 4-53: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC204 AND dsPIC33EPXXXGP/MC204/504 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 105 TABLE 4-56: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC203 AND dsPIC33EPXXXGP/MC203/503 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 106 TABLE 4-59: PORTA REGISTER MAP FOR PIC24EPXXXGP/MC202 AND dsPIC33EPXXXGP/MC202/502 DEVICES ONLY File Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name...
  • Page 107 EA[15] Generate DSRPAG[9] PSV Address = 1? Select DSRPAG DSRPAG[8:0] 9 Bits 15 Bits 24-Bit EDS EA Byte Select Note: DS read access when DSRPAG = 0x000 will force an address error trap.  2011-2020 Microchip Technology Inc. DS70000657J-page 107...
  • Page 108 EDS only. The Data Space and EDS can be read from, address space in the EDS and 8 Mbytes (DSRPAG and written to, using DSRPAG and DSWPAG, only) of PSV address space. The paged data memory respectively. space is shown in Example 4-3.  2011-2020 Microchip Technology Inc. DS70000657J-page 108...
  • Page 109 EXAMPLE 4-3: PAGED DATA MEMORY SPACE Local Data Space Program Space Table Address Space (DSRPAG[9:0]/DSWPAG[8:0]) (Instruction & Data) (TBLPAG[7:0]) DS_Addr[14:0] 0x0000 Page 0 Reserved DS_Addr[15:0] (Will produce an 0x0000 address error trap) 0x7FFF (TBLPAG = 0x00) 0x0000 lsw Using EDS Page 0x001 Program Memory TBLRDL/TBLWTL (DSRPAG = 0x001)
  • Page 110 An EDS access with DSxPAG = 0x000 will generate an address error trap. Only reads from PS are supported using DSRPAG. An attempt to write to PS using DSWPAG will generate an address error trap. Pseudolinear Addressing is not supported for large offsets.  2011-2020 Microchip Technology Inc. DS70000657J-page 110...
  • Page 111 DS Address 0x008000 PAGE 1 0xFFFF 0x010000 PAGE 2 0x018000 PAGE 3 DSRPAG[9] = 0 EDS EA Address (24 bits) (DSRPAG[8:0], EA[14:0]) (DSWPAG[8:0], EA[14:0]) 0xFE8000 PAGE 1FD 0xFF0000 PAGE 1FE 0xFF8000 PAGE 1FF  2011-2020 Microchip Technology Inc. DS70000657J-page 111...
  • Page 112 All other values of MSTRPR[15:0] are being highest and M3 being lowest, with M2 in reserved. between). Also, all the bus masters with priorities below FIGURE 4-18: ARBITER ARCHITECTURE Reserved MSTRPR[15:0] Data Memory Arbiter SRAM  2011-2020 Microchip Technology Inc. DS70000657J-page 112...
  • Page 113 4-19. During exception processing, the MSB of the PC is concatenated with the lower 8 bits of the CPU STATUS Register, SR. This allows the contents of SRL to be preserved automatically during interrupt processing.  2011-2020 Microchip Technology Inc. DS70000657J-page 113...
  • Page 114 EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.  2011-2020 Microchip Technology Inc. DS70000657J-page 114...
  • Page 115 DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ULNK, the source of an operand or result is implied by the opcode itself. Certain operations, such as a NOP, do not have any operands.  2011-2020 Microchip Technology Inc. DS70000657J-page 115...
  • Page 116 AGAIN, #0x31 ;fill the 50 buffer locations W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Start Addr = 0x1100 End Addr = 0x1163 Length = 50 words  2011-2020 Microchip Technology Inc. DS70000657J-page 116...
  • Page 117 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 Bit-Reversed Address Pivot Point XBREV[14:0] = 0x0008 for a 16-Word Bit-Reversed Buffer  2011-2020 Microchip Technology Inc. DS70000657J-page 117...
  • Page 118 AND PIC24EPXXXGP/MC20X TABLE 4-64: BIT-REVERSED ADDRESSING SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address Decimal Decimal  2011-2020 Microchip Technology Inc. DS70000657J-page 118...
  • Page 119 The Least Significant bit (LSb) of Program Space addresses is always fixed as ‘0’ to maintain word alignment of data in the Program and Data Spaces. Table operations are not required to be word-aligned. Table Read operations are permitted in the configuration memory space.  2011-2020 Microchip Technology Inc. DS70000657J-page 119...
  • Page 120 The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in 0x800000 the user memory area.  2011-2020 Microchip Technology Inc. DS70000657J-page 120...
  • Page 121: Flash Program Memory

    (one of the FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 Bits Using Program Counter Program Counter Working Reg EA Using TBLPAG Reg Table Instruction 8 Bits 16 Bits User/Configuration Byte 24-Bit EA Space Select Select  2011-2020 Microchip Technology Inc. DS70000657J-page 121...
  • Page 122 DS70000609) “dsPIC33/PIC24 Family bits of the EA, while the NVMADRL register is used to Reference Manual” for details and codes examples on hold the lower 16 bits of the EA. programming using RTSP.  2011-2020 Microchip Technology Inc. DS70000657J-page 122...
  • Page 123 Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress. Two adjacent words on a 4-word boundary are programmed during execution of this operation. This bit can only be reset on a POR or a BOR.  2011-2020 Microchip Technology Inc. DS70000657J-page 123...
  • Page 124 -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY[7:0]: Key Register (write-only) bits  2011-2020 Microchip Technology Inc. DS70000657J-page 124...
  • Page 125: Resets

    - Security Reset FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR Module Sleep or Idle Internal SYSRST Regulator Rise Detect Trap Conflict Illegal Opcode Uninitialized W Register Security Reset Configuration Mismatch  2011-2020 Microchip Technology Inc. DS70000657J-page 125...
  • Page 126 In the event you are not able to access the product page using the link above, enter • All Related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en555464  2011-2020 Microchip Technology Inc. DS70000657J-page 126...
  • Page 127 All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.  2011-2020 Microchip Technology Inc. DS70000657J-page 127...
  • Page 128 All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.  2011-2020 Microchip Technology Inc. DS70000657J-page 128...
  • Page 129: Interrupt Controller

    Each Interrupt or Exception Source programmed with the address of a default • Fixed Priority within a Specified User Priority interrupt handler routine that contains a Level RESET instruction. • Fixed Interrupt Entry and Return Latencies  2011-2020 Microchip Technology Inc. DS70000657J-page 129...
  • Page 130 Interrupt Vector Details Interrupt Vector 116 0x0000FC Interrupt Vector 117 0x0000FE Interrupt Vector 118 0x000100 Interrupt Vector 119 0x000102 Interrupt Vector 120 0x000104 Interrupt Vector 244 0x0001FC Interrupt Vector 245 0x0001FE START OF CODE 0x000200  2011-2020 Microchip Technology Inc. DS70000657J-page 130...
  • Page 131 PWMSpEventMatch – PWM Special 0x000086 IFS3[9] IEC3[9] IPC14[6:4] Event Match Note 1: This interrupt source is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only. This interrupt source is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.  2011-2020 Microchip Technology Inc. DS70000657J-page 131...
  • Page 132 159-245 151-245 0x000142-0x0001FE — — — Lowest Natural Order Priority Note 1: This interrupt source is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only. This interrupt source is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.  2011-2020 Microchip Technology Inc. DS70000657J-page 132...
  • Page 133 The INTCON4 register contains the Software-Generated Hard Trap (SGHT) status bit. All Interrupt registers are described in Register 7-3 through Register 7-7 in the following pages.  2011-2020 Microchip Technology Inc. DS70000657J-page 133...
  • Page 134 Level. The value in parentheses indicates the IPL, if IPL[3] = 1. User interrupts are disabled when IPL[3] = 1. The IPL[2:0] Status bits are read-only when the NSTDIS bit (INTCON1[15]) = 1.  2011-2020 Microchip Technology Inc. DS70000657J-page 134...
  • Page 135 0 = CPU Interrupt Priority Level is 7 or less Note 1: For complete register details, see Register 3-2. The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level.  2011-2020 Microchip Technology Inc. DS70000657J-page 135...
  • Page 136 0 = Math error trap was not caused by a divide-by-zero bit 5 DMACERR: DMAC Trap Flag bit 1 = DMAC trap has occurred 0 = DMAC trap has not occurred Note 1: These bits are available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.  2011-2020 Microchip Technology Inc. DS70000657J-page 136...
  • Page 137 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ Note 1: These bits are available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.  2011-2020 Microchip Technology Inc. DS70000657J-page 137...
  • Page 138 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge  2011-2020 Microchip Technology Inc. DS70000657J-page 138...
  • Page 139 = Bit is unknown bit 15-1 Unimplemented: Read as ‘0’ bit 0 SGHT: Software-Generated Hard Trap Status bit 1 = Software-generated hard trap has occurred 0 = Software-generated hard trap has not occurred  2011-2020 Microchip Technology Inc. DS70000657J-page 139...
  • Page 140 00000101 = 5, DMAC error trap 00000100 = 4, Math error trap 00000011 = 3, Stack error trap 00000010 = 2, Generic hard trap 00000001 = 1, Address error trap 00000000 = 0, Oscillator fail trap  2011-2020 Microchip Technology Inc. DS70000657J-page 140...
  • Page 141: Direct Memory Access (Dma)

    Refer to Table 8-1 for a complete list of supported this data sheet for device-specific register peripherals. and bit information. FIGURE 8-1: DMA CONTROLLER MODULE Data Memory PERIPHERAL Arbiter (see Figure 4-18) SRAM  2011-2020 Microchip Technology Inc. DS70000657J-page 141...
  • Page 142 UART2TX – UART2 Transmitter — 0x0234 (U2TXREG) 00011111 ECAN1 – RX Data Ready 0x0440 (C1RXD) — 00100010 ECAN1 – TX Data Request — 0x0442 (C1TXD) 01000110 ADC1 – ADC1 Convert Done 0x0300 (ADC1BUF0) — 00001101  2011-2020 Microchip Technology Inc. DS70000657J-page 142...
  • Page 143 IECx register in the interrupt controller, and the cor- • All Related “dsPIC33/PIC24 Family Reference responding interrupt priority control bits (DMAxIP) are Manual” Sections located in an IPCx register in the interrupt controller. • Development Tools  2011-2020 Microchip Technology Inc. DS70000657J-page 143...
  • Page 144 11 = One-Shot, Ping-Pong modes are enabled (one block transfer from/to each DMA buffer) 10 = Continuous, Ping-Pong modes are enabled 01 = One-Shot, Ping-Pong modes are disabled 00 = Continuous, Ping-Pong modes are disabled  2011-2020 Microchip Technology Inc. DS70000657J-page 144...
  • Page 145 The FORCE bit cannot be cleared by user software. The FORCE bit is cleared by hardware when the forced DMA transfer is complete or the channel is disabled (CHEN = 0). This selection is available in dsPIC33EPXXXGP/MC50X devices only.  2011-2020 Microchip Technology Inc. DS70000657J-page 145...
  • Page 146 U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STA[15:0]: Primary Start Address bits (source or destination)  2011-2020 Microchip Technology Inc. DS70000657J-page 146...
  • Page 147 U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STB[15:0]: Secondary Start Address bits (source or destination)  2011-2020 Microchip Technology Inc. DS70000657J-page 147...
  • Page 148 If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. The number of DMA transfers = CNT[13:0] + 1.  2011-2020 Microchip Technology Inc. DS70000657J-page 148...
  • Page 149 U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DSADR[15:0]: Most Recent DMA Address Accessed by DMA bits  2011-2020 Microchip Technology Inc. DS70000657J-page 149...
  • Page 150 1 = Write collision is detected 0 = No write collision is detected bit 0 PWCOL0: DMA Channel 0 Peripheral Write Collision Flag bit 1 = Write collision is detected 0 = No write collision is detected  2011-2020 Microchip Technology Inc. DS70000657J-page 150...
  • Page 151 0 = No request collision is detected bit 0 RQCOL0: DMA Channel 0 Transfer Request Collision Flag bit 1 = User force and interrupt-based request collision is detected 0 = No request collision is detected  2011-2020 Microchip Technology Inc. DS70000657J-page 151...
  • Page 152 0011 = Last data transfer was handled by Channel 3 0010 = Last data transfer was handled by Channel 2 0001 = Last data transfer was handled by Channel 1 0000 = Last data transfer was handled by Channel 0  2011-2020 Microchip Technology Inc. DS70000657J-page 152...
  • Page 153 1 = DMASTB1 register is selected 0 = DMASTA1 register is selected bit 0 PPST0: DMA Channel 0 Ping-Pong Mode Status Flag bit 1 = DMASTB0 register is selected 0 = DMASTA0 register is selected  2011-2020 Microchip Technology Inc. DS70000657J-page 153...
  • Page 154 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 154...
  • Page 155: Oscillator Configuration

    Throughout this document, F and F are used interchangeably, except in the case of Doze mode. F will be different when Doze mode is used with a doze ratio of 1:2 or lower.  2011-2020 Microchip Technology Inc. DS70000657J-page 155...
  • Page 156 N2 = 2 x (PLLPOST + 1) M = PLLDIV + 2 EQUATION 9-3: CALCULATION   PLLDIV       Fvco ------ - ------------------------------------ -       PLLPRE  2011-2020 Microchip Technology Inc. DS70000657J-page 156...
  • Page 157 In the event you are not able to access the product page using the link above, enter • All Related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en555464  2011-2020 Microchip Technology Inc. DS70000657J-page 157...
  • Page 158 FRC mode as a transitional clock source between the two PLL modes. This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an actual oscillator failure and trigger an oscillator failure trap.  2011-2020 Microchip Technology Inc. DS70000657J-page 158...
  • Page 159 FRC mode as a transitional clock source between the two PLL modes. This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an actual oscillator failure and trigger an oscillator failure trap.  2011-2020 Microchip Technology Inc. DS70000657J-page 159...
  • Page 160 This bit is cleared when the ROI bit is set and an interrupt occurs. The DOZEN bit cannot be set if DOZE[2:0] = 000. If DOZE[2:0] = 000, any attempt by user software to set the DOZEN bit is ignored.  2011-2020 Microchip Technology Inc. DS70000657J-page 160...
  • Page 161 This bit is cleared when the ROI bit is set and an interrupt occurs. The DOZEN bit cannot be set if DOZE[2:0] = 000. If DOZE[2:0] = 000, any attempt by user software to set the DOZEN bit is ignored.  2011-2020 Microchip Technology Inc. DS70000657J-page 161...
  • Page 162 PLLDIV[8:0]: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 111111111 = 513 • • • 000110000 = 50 (default) • • • 000000010 = 4 000000001 = 3 000000000 = 2  2011-2020 Microchip Technology Inc. DS70000657J-page 162...
  • Page 163 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency – 0.047% (7.367 MHz) • • • 100001 = Center frequency – 1.453% (7.263 MHz) 100000 = Minimum frequency deviation of -1.5% (7.259 MHz)  2011-2020 Microchip Technology Inc. DS70000657J-page 163...
  • Page 164 Unimplemented: Read as ‘0’ Note 1: The Reference Oscillator output must be disabled (ROON = 0) before writing to these bits. This pin is remappable. See Section 11.4 “Peripheral Pin Select (PPS)” for more information.  2011-2020 Microchip Technology Inc. DS70000657J-page 164...
  • Page 165: Power-Saving Features

    ; Put the device into Sleep mode Note 1: The use of PWRSV #SLEEP_MODE has limitations when the Flash Voltage Regulator bit, VREGSF (RCON[11]), is set to Standby mode. Refer to Section 10.2.1 “Sleep Mode” for more information.  2011-2020 Microchip Technology Inc. DS70000657J-page 165...
  • Page 166 • Any form of device Reset • A WDT time-out EXAMPLE 10-2: SLEEP MODE PWRSAV INSTRUCTION SYNTAX (WITH FLASH VOLTAGE REGULATOR SET TO STANDBY MODE) .global _GoToSleep .section .text .align _GoToSleep: PWRSAV #SLEEP_MODE TO_FLUSH_QUEUE_LABEL TO_FLUSH_QUEUE_LABEL: RETURN  2011-2020 Microchip Technology Inc. DS70000657J-page 166...
  • Page 167 In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed, while the CPU clock speed is  2011-2020 Microchip Technology Inc. DS70000657J-page 167...
  • Page 168 In the event you are not able to access the • Webinars product page using the link above, enter this URL in your browser: • All Related “dsPIC33/PIC24 Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en555464 • Development Tools  2011-2020 Microchip Technology Inc. DS70000657J-page 168...
  • Page 169 1 = SPI2 module is disabled 0 = SPI2 module is enabled Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. This bit is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only.  2011-2020 Microchip Technology Inc. DS70000657J-page 169...
  • Page 170 1 = ADC1 module is disabled 0 = ADC1 module is enabled Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. This bit is available on dsPIC33EPXXXGP50X and dsPIC33EPXXXMC50X devices only.  2011-2020 Microchip Technology Inc. DS70000657J-page 170...
  • Page 171 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled  2011-2020 Microchip Technology Inc. DS70000657J-page 171...
  • Page 172 1 = Reference clock module is disabled 0 = Reference clock module is enabled bit 2 CTMUMD: CTMU Module Disable bit 1 = CTMU module is disabled 0 = CTMU module is enabled bit 1-0 Unimplemented: Read as ‘0’  2011-2020 Microchip Technology Inc. DS70000657J-page 172...
  • Page 173 PWM1MD: PWM1 Module Disable bit 1 = PWM1 module is disabled 0 = PWM1 module is enabled bit 7-0 Unimplemented: Read as ‘0’ Note 1: This bit is available on dsPIC33EPXXXMC50X/20X and PIC24EPXXXMC20X devices only.  2011-2020 Microchip Technology Inc. DS70000657J-page 173...
  • Page 174 PTGMD: PTG Module Disable bit 1 = PTG module is disabled 0 = PTG module is enabled bit 2-0 Unimplemented: Read as ‘0’ Note 1: This single bit enables and disables all four DMA channels.  2011-2020 Microchip Technology Inc. DS70000657J-page 174...
  • Page 175: I/O Ports

    Peripheral Output Enable Output Enable Peripheral Output Data PIO Module Output Data Read TRIS Data Bus I/O Pin WR TRIS TRIS Latch WR LAT + WR Port Data Latch Read LAT Input Data Read Port  2011-2020 Microchip Technology Inc. DS70000657J-page 175...
  • Page 176 One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be a NOP, as shown in Example 11-1.  2011-2020 Microchip Technology Inc. DS70000657J-page 176...
  • Page 177 The peripherals managed by the Peripheral Pin Select are all digital-only peripherals. These include general serial communications (UART and SPI), general pur- pose timer clock inputs, timer-related peripherals (input capture and output compare) and interrupt-on-change inputs.  2011-2020 Microchip Technology Inc. DS70000657J-page 177...
  • Page 178 /* Connect the IC1 input to the digital filter on the FHOME1 input */ QEI1IOC = 0x4000; /* Enable the QEI digital filter */ QEI1CON = 0x8000; /* Enable the QEI module */  2011-2020 Microchip Technology Inc. DS70000657J-page 178...
  • Page 179 Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. This input source is available on dsPIC33EPXXXGP/MC50X devices only. This input source is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.  2011-2020 Microchip Technology Inc. DS70000657J-page 179...
  • Page 180 Legend: Shaded rows indicate PPS Input register values that are unimplemented. Note 1: Section 11.4.4.1 “Virtual Connections” for more information on selecting this pin assignment. These inputs are available on dsPIC33EPXXXGP/MC50X devices only.  2011-2020 Microchip Technology Inc. DS70000657J-page 180...
  • Page 181 Legend: Shaded rows indicate PPS Input register values that are unimplemented. Note 1: Section 11.4.4.1 “Virtual Connections” for more information on selecting this pin assignment. These inputs are available on dsPIC33EPXXXGP/MC50X devices only.  2011-2020 Microchip Technology Inc. DS70000657J-page 181...
  • Page 182 RPn tied to Reference Clock Output 110001 C4OUT RPn tied to Comparator Output 4 110010 Note 1: This function is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. This function is available in dsPIC33EPXXXGP/MC50X devices only.  2011-2020 Microchip Technology Inc. DS70000657J-page 182...
  • Page 183 The internal pull-up is up to – 0.8), not V . This value is still above the minimum V of CMOS and TTL devices.  2011-2020 Microchip Technology Inc. DS70000657J-page 183...
  • Page 184 “dsPIC33/PIC24 Family Reference Manual” any “digital input(s)” on a corresponding pin, no • Code Samples exceptions. • Application Notes • Software Libraries • Webinars • All Related “dsPIC33/PIC24 Family Reference Manual” Sections • Development Tools  2011-2020 Microchip Technology Inc. DS70000657J-page 184...
  • Page 185 Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 • • • 0000001 = Input tied to CMP1 0000000 = Input tied to V bit 7-0 Unimplemented: Read as ‘0’  2011-2020 Microchip Technology Inc. DS70000657J-page 185...
  • Page 186 T2CKR[6:0]: Assign Timer2 External Clock (T2CK) to the Corresponding RPn pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 • • • 0000001 = Input tied to CMP1 0000000 = Input tied to V  2011-2020 Microchip Technology Inc. DS70000657J-page 186...
  • Page 187 IC1R[6:0]: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 • • • 0000001 = Input tied to CMP1 0000000 = Input tied to V  2011-2020 Microchip Technology Inc. DS70000657J-page 187...
  • Page 188 IC3R[6:0]: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 • • • 0000001 = Input tied to CMP1 0000000 = Input tied to V  2011-2020 Microchip Technology Inc. DS70000657J-page 188...
  • Page 189 OCFAR[6:0]: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 • • • 0000001 = Input tied to CMP1 0000000 = Input tied to V  2011-2020 Microchip Technology Inc. DS70000657J-page 189...
  • Page 190 FLT1R[6:0]: Assign PWM Fault 1 (FLT1) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 • • • 0000001 = Input tied to CMP1 0000000 = Input tied to V  2011-2020 Microchip Technology Inc. DS70000657J-page 190...
  • Page 191 QEA1R[6:0]: Assign A (QEA) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 • • • 0000001 = Input tied to CMP1 0000000 = Input tied to V  2011-2020 Microchip Technology Inc. DS70000657J-page 191...
  • Page 192 IND1XR[6:0]: Assign QEI1 INDEX1 (INDX1) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 • • • 0000001 = Input tied to CMP1 0000000 = Input tied to V  2011-2020 Microchip Technology Inc. DS70000657J-page 192...
  • Page 193 U2RXR[6:0]: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 • • • 0000001 = Input tied to CMP1 0000000 = Input tied to V  2011-2020 Microchip Technology Inc. DS70000657J-page 193...
  • Page 194 SDI2R[6:0]: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 • • • 0000001 = Input tied to CMP1 0000000 = Input tied to V  2011-2020 Microchip Technology Inc. DS70000657J-page 194...
  • Page 195 C1RXR[6:0]: Assign CAN1 RX Input (CRX1) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 • • • 0000001 = Input tied to CMP1 0000000 = Input tied to V  2011-2020 Microchip Technology Inc. DS70000657J-page 195...
  • Page 196 Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 • • • 0000001 = Input tied to CMP1 0000000 = Input tied to V bit 7-0 Unimplemented: Read as ‘0’  2011-2020 Microchip Technology Inc. DS70000657J-page 196...
  • Page 197 Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 • • • 0000001 = Input tied to CMP1 0000000 = Input tied to V bit 7-0 Unimplemented: Read as ‘0’  2011-2020 Microchip Technology Inc. DS70000657J-page 197...
  • Page 198 DTCMP2R[6:0]: Assign PWM Dead-Time Compensation Input 2 (DTCMP2) to the Corresponding RPn Pin bits (see Table 11-2 for input pin selection numbers) 1111001 = Input tied to RPI121 • • • 0000001 = Input tied to CMP1 0000000 = Input tied to V  2011-2020 Microchip Technology Inc. DS70000657J-page 198...
  • Page 199 (see Table 11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP36R[5:0]: Peripheral Output Function is Assigned to RP36 Output Pin bits (see Table 11-3 for peripheral function numbers)  2011-2020 Microchip Technology Inc. DS70000657J-page 199...
  • Page 200 (see Table 11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP40R[5:0]: Peripheral Output Function is Assigned to RP40 Output Pin bits (see Table 11-3 for peripheral function numbers)  2011-2020 Microchip Technology Inc. DS70000657J-page 200...
  • Page 201 (see Table 11-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP54R[5:0]: Peripheral Output Function is Assigned to RP54 Output Pin bits (see Table 11-3 for peripheral function numbers)  2011-2020 Microchip Technology Inc. DS70000657J-page 201...
  • Page 202 = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP97R[5:0]: Peripheral Output Function is Assigned to RP97 Output Pin bits (see Table 11-3 for peripheral function numbers) bit 7-0 Unimplemented: Read as ‘0’  2011-2020 Microchip Technology Inc. DS70000657J-page 202...
  • Page 203 ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 RP120R[5:0]: Peripheral Output Function is Assigned to RP120 Output Pin bits (see Table 11-3 for peripheral function numbers)  2011-2020 Microchip Technology Inc. DS70000657J-page 203...
  • Page 204 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 204...
  • Page 205: Timer1

    Sync Detect Set T1IF Flag Prescaler T1CLK (/n) TGATE Data Reset TMR1 Latch TCKPS[1:0] T1CK Equal Prescaler Comparator Sync (/n) CTMU Edge Control Logic TGATE TSYNC TCKPS[1:0] Note 1: is the peripheral clock.  2011-2020 Microchip Technology Inc. DS70000657J-page 205...
  • Page 206 In the event you are not able to access the product page using the link above, enter • All Related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/wwwproducts/ • Development Tools Devices.aspx?dDocName=en555464  2011-2020 Microchip Technology Inc. DS70000657J-page 206...
  • Page 207 Note 1: When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any attempts by user software to write to the TMR1 register are ignored.  2011-2020 Microchip Technology Inc. DS70000657J-page 207...
  • Page 208 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 208...
  • Page 209: Timer2/3 And Timer4/5

    • Interrupt on a 32-Bit Period Register Match • Time Base for Input Capture and Output Compare Modules (Timer2 and Timer3 only) • ADC1 Event Trigger (32-bit timer pairs, and Timer3 and Timer5 only)  2011-2020 Microchip Technology Inc. DS70000657J-page 209...
  • Page 210 Reset TMRx Latch TCKPS[1:0] TxCK Prescaler Sync (/n) Equal Comparator ADC Start of Conversion Trigger TGATE TCKPS[1:0] Note 1: is the peripheral clock. The ADC trigger is available on TMR3 and TMR5 only.  2011-2020 Microchip Technology Inc. DS70000657J-page 210...
  • Page 211 In the event you are not able to access the product page using the link above, enter • All Related “dsPIC33/PIC24 Family Reference this URL in your browser: Manual” Sections http://www.microchip.com/ • Development Tools wwwproducts/Devices.aspx?d DocName=en555464  2011-2020 Microchip Technology Inc. DS70000657J-page 211...
  • Page 212 1 = External clock is from pin, TxCK (on the rising edge) 0 = Internal clock (F bit 0 Unimplemented: Read as ‘0’ Note 1: The TxCK pin is not available on all devices. See the “Pin Diagrams” section for the available pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 212...
  • Page 213 When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON[3]), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. The TyCK pin is not available on all devices. See the “Pin Diagrams” section for the available pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 213...
  • Page 214 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 214...
  • Page 215: Input Capture

    The Trigger/Sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for proper ICx module operation or the Trigger/Sync source must be changed to another source option.  2011-2020 Microchip Technology Inc. DS70000657J-page 215...
  • Page 216 In the event you are not able to access the • Webinars product page using the link above, enter this URL in your browser: • All Related “dsPIC33/PIC24 Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en555464 • Development Tools  2011-2020 Microchip Technology Inc. DS70000657J-page 216...
  • Page 217 010 = Capture mode, every falling edge (Simple Capture mode) 001 = Capture mode, every edge rising and falling (Edge Detect mode (ICI[1:0]) is not used in this mode) 000 = Input capture module is turned off  2011-2020 Microchip Technology Inc. DS70000657J-page 217...
  • Page 218 Each Input Capture x (ICx) module has one PTG input source. See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for more information. PTGO8 = IC1 PTGO9 = IC2 PTGO10 = IC3 PTGO11 = IC4  2011-2020 Microchip Technology Inc. DS70000657J-page 218...
  • Page 219 Each Input Capture x (ICx) module has one PTG input source. See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for more information. PTGO8 = IC1 PTGO9 = IC2 PTGO10 = IC3 PTGO11 = IC4  2011-2020 Microchip Technology Inc. DS70000657J-page 219...
  • Page 220 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 220...
  • Page 221: Output Compare

    The Trigger/Sync source is enabled by default and is set to Timer2 as a source. This timer must be enabled for proper OCx module operation or the Trigger/Sync source must be changed to another source option.  2011-2020 Microchip Technology Inc. DS70000657J-page 221...
  • Page 222 In the event you are not able to access the • Webinars product page using the link above, enter this URL in your browser: • All Related “dsPIC33/PIC24 Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en555464 • Development Tools  2011-2020 Microchip Technology Inc. DS70000657J-page 222...
  • Page 223 Each Output Compare x module (OCx) has one PTG clock source. See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for more information. PTGO4 = OC1 PTGO5 = OC2 PTGO6 = OC3 PTGO7 = OC4  2011-2020 Microchip Technology Inc. DS70000657J-page 223...
  • Page 224 Each Output Compare x module (OCx) has one PTG clock source. See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for more information. PTGO4 = OC1 PTGO5 = OC2 PTGO6 = OC3 PTGO7 = OC4  2011-2020 Microchip Technology Inc. DS70000657J-page 224...
  • Page 225 Each Output Compare x module (OCx) has one PTG Trigger/Synchronization source. See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for more information. PTGO0 = OC1 PTGO1 = OC2 PTGO2 = OC3 PTGO3 = OC4  2011-2020 Microchip Technology Inc. DS70000657J-page 225...
  • Page 226 Each Output Compare x module (OCx) has one PTG Trigger/Synchronization source. See Section 24.0 “Peripheral Trigger Generator (PTG) Module” for more information. PTGO0 = OC1 PTGO1 = OC2 PTGO2 = OC3 PTGO3 = OC4  2011-2020 Microchip Technology Inc. DS70000657J-page 226...
  • Page 227: High-Speed Pwm Module (Dspic33Epxxxmc20X/50X And Pic24Epxxxmc20X Devices Only)

    The Fault mode may be changed using • PWM Capture Functionality the FLTMOD[1:0] bits (FCLCON[1:0]), regardless of the state of FLT32. Note: In Edge-Aligned PWM mode, the duty cycle, dead time, phase shift and frequency resolution are 7.14 ns.  2011-2020 Microchip Technology Inc. DS70000657J-page 227...
  • Page 228 ; Load desired value of IOCON1 register in w0 mov w10, PWMKEY ; Write first unlock key to PWMKEY register mov w11, PWMKEY ; Write second unlock key to PWMKEY register mov w0,IOCON1 ; Write desired value to IOCON1 register  2011-2020 Microchip Technology Inc. DS70000657J-page 228...
  • Page 229 Note 1: The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the given PWM generator. Refer to “High-Speed PWM” (www.microchip.com/DS70645) in the “dsPIC33/PIC24 Family Reference Manual” for more information.  2011-2020 Microchip Technology Inc. DS70000657J-page 229...
  • Page 230 Note 1: The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the given PWM generator. Refer to “High-Speed PWM” (www.microchip.com/DS70645) in the “dsPIC33/PIC24 Family Reference Manual” for more information.  2011-2020 Microchip Technology Inc. DS70000657J-page 230...
  • Page 231 In the event you are not able to access the • Webinars product page using the link above, enter this URL in your browser: • All Related “dsPIC33/PIC24 Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en555464 • Development Tools  2011-2020 Microchip Technology Inc. DS70000657J-page 231...
  • Page 232 Section 24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.  2011-2020 Microchip Technology Inc. DS70000657J-page 232...
  • Page 233 Section 24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.  2011-2020 Microchip Technology Inc. DS70000657J-page 233...
  • Page 234 001 = Divide-by-2 000 = Divide-by-1, maximum PWMx timing resolution (power-on default) Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results.  2011-2020 Microchip Technology Inc. DS70000657J-page 234...
  • Page 235 U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 SEVTCMP[15:0]: Special Event Compare Count Value bits  2011-2020 Microchip Technology Inc. DS70000657J-page 235...
  • Page 236 U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 MDC[15:0]: PWMx Master Duty Cycle Value bits  2011-2020 Microchip Technology Inc. DS70000657J-page 236...
  • Page 237 ‘0’. When the local time base counter matches the value specified by the user in the TRIGx register, an ADC trigger signal is generated. Also, see the TRIGx register description.  2011-2020 Microchip Technology Inc. DS70000657J-page 237...
  • Page 238 ‘0’. When the local time base counter matches the value specified by the user in the TRIGx register, an ADC trigger signal is generated. Also, see the TRIGx register description.  2011-2020 Microchip Technology Inc. DS70000657J-page 238...
  • Page 239 2: If ITB (PWMCONx[9]) = 1, the following applies based on the mode of operation: Complementary, Redundant and Push-Pull Output mode (PMOD[1:0] (IOCONx[11:10]) = 00, 01 or 10), PHASEx[15:0] = Independent time base period value for PWMxH and PWMxL  2011-2020 Microchip Technology Inc. DS70000657J-page 239...
  • Page 240 ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 ALTDTRx[13:0]: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits  2011-2020 Microchip Technology Inc. DS70000657J-page 240...
  • Page 241 000001 = Waits 1 PWM cycle before generating the first trigger event after the module is enabled 000000 = Waits 0 PWM cycles before generating the first trigger event after the module is enabled Note 1: The secondary PWM generator cannot generate PWMx trigger interrupts.  2011-2020 Microchip Technology Inc. DS70000657J-page 241...
  • Page 242 The OSYNC bit (IOCON[0]) must be set to ‘1’ prior to changing the state of the SWAP bit (IOCON[1]), else the SWAP function will attempt to occur in the middle of the PWM cycle and unpredictable results may occur.  2011-2020 Microchip Technology Inc. DS70000657J-page 242...
  • Page 243 The OSYNC bit (IOCON[0]) must be set to ‘1’ prior to changing the state of the SWAP bit (IOCON[1]), else the SWAP function will attempt to occur in the middle of the PWM cycle and unpredictable results may occur.  2011-2020 Microchip Technology Inc. DS70000657J-page 243...
  • Page 244 = Bit is unknown bit 15-0 TRGCMP[15:0]: Trigger Control Value bits When the primary PWMx functions in local time base, this register contains the compare values that can trigger the ADC module.  2011-2020 Microchip Technology Inc. DS70000657J-page 244...
  • Page 245 If the PWMLOCK Configuration bit (FOSCSEL[6]) is a ‘1’, the IOCONx register can only be written after the unlock sequence has been executed. These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results.  2011-2020 Microchip Technology Inc. DS70000657J-page 245...
  • Page 246 If the PWMLOCK Configuration bit (FOSCSEL[6]) is a ‘1’, the IOCONx register can only be written after the unlock sequence has been executed. These bits should be changed only when PTEN = 0. Changing the clock selection during operation will yield unpredictable results.  2011-2020 Microchip Technology Inc. DS70000657J-page 246...
  • Page 247 1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is low 0 = No blanking when PWMxL output is low Note 1: The blanking signal is selected via the BLANKSELx bits in the AUXCONx register.  2011-2020 Microchip Technology Inc. DS70000657J-page 247...
  • Page 248 ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 LEB[11:0]: Leading-Edge Blanking Delay for Current-Limit and Fault Inputs bits  2011-2020 Microchip Technology Inc. DS70000657J-page 248...
  • Page 249 1 = PWMxH chopping function is enabled 0 = PWMxH chopping function is disabled bit 0 CHOPLEN: PWMxL Output Chopping Enable bit 1 = PWMxL chopping function is enabled 0 = PWMxL chopping function is disabled  2011-2020 Microchip Technology Inc. DS70000657J-page 249...
  • Page 250 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 250...
  • Page 251: Quadrature Encoder Interface (Qei) Module (Dspic33Epxxxmc20X/50X And Pic24Epxxxmc20X Devices Only)

    Figure 17-1 illustrates the QEI block diagram. available on all devices. Refer to Section 4.0 “Memory Organization” this data sheet for device-specific register and bit information.  2011-2020 Microchip Technology Inc. DS70000657J-page 251...
  • Page 252 FIGURE 17-1: QEI BLOCK DIAGRAM FLTREN GATEN FHOMEx HOMEx GATE  COUNT QFDIV COUNT EXTCNT DIVCLK INDXx FINDXx Digital Filter Quadrature QEBx COUNT GATE Decoder 1’b0 Logic CNTPOL EXTCNT QEAx GATE PCHGE PCLLE CNTCMPx PCLLE PCHEQ PCLEQ PCHGE 32-Bit Less Than 32-Bit Greater Than or Equal Comparator or Equal Comparator...
  • Page 253 In the event you are not able to access the • Webinars product page using the link above, enter this URL in your browser: • All Related “dsPIC33/PIC24 Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en555464 • Development Tools  2011-2020 Microchip Technology Inc. DS70000657J-page 253...
  • Page 254 POSCNTL registers are reset. QEA/QEB signals used for the index match have swap and polarity values applied, as determined by the SWPAB and QEAPOL/QEBPOL bits. The selected clock rate should be at least twice the expected maximum quadrature count rate.  2011-2020 Microchip Technology Inc. DS70000657J-page 254...
  • Page 255 POSCNTL registers are reset. QEA/QEB signals used for the index match have swap and polarity values applied, as determined by the SWPAB and QEAPOL/QEBPOL bits. The selected clock rate should be at least twice the expected maximum quadrature count rate.  2011-2020 Microchip Technology Inc. DS70000657J-page 255...
  • Page 256 1 = Input is inverted 0 = Input is not inverted bit 3 HOME: Status of HOMEx Input Pin After Polarity Control bit 1 = Pin is at logic ‘1’ 0 = Pin is at logic ‘0’  2011-2020 Microchip Technology Inc. DS70000657J-page 256...
  • Page 257 0 = Pin is at logic ‘0’ bit 0 QEA: Status of QEAx Input Pin After Polarity Control And SWPAB Pin Swapping bit 1 = Pin is at logic ‘1’ 0 = Pin is at logic ‘0’  2011-2020 Microchip Technology Inc. DS70000657J-page 257...
  • Page 258 HOMIRQ: Status Flag for Home Event Status bit 1 = Home event has occurred 0 = No Home event has occurred Note 1: This status bit is only applicable to PIMOD[2:0] modes, ‘011’ and ‘100’.  2011-2020 Microchip Technology Inc. DS70000657J-page 258...
  • Page 259 0 IDXIEN: Index Input Event Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: This status bit is only applicable to PIMOD[2:0] modes, ‘011’ and ‘100’.  2011-2020 Microchip Technology Inc. DS70000657J-page 259...
  • Page 260 U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 POSHLD[15:0]: Hold Register for Reading and Writing POS1CNTH bits  2011-2020 Microchip Technology Inc. DS70000657J-page 260...
  • Page 261 -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INDXCNT[15:0]: Low Word Used to Form 32-Bit Index Counter Register (INDX1CNT) bits  2011-2020 Microchip Technology Inc. DS70000657J-page 261...
  • Page 262 -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEIIC[15:0]: Low Word Used to Form 32-Bit Initialization/Capture Register (QEI1IC) bits  2011-2020 Microchip Technology Inc. DS70000657J-page 262...
  • Page 263 -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEILEC[15:0]: Low Word Used to Form 32-Bit Less Than or Equal Compare Register (QEI1LEC) bits  2011-2020 Microchip Technology Inc. DS70000657J-page 263...
  • Page 264 -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 QEIGEC[15:0]: Low Word Used to Form 32-Bit Greater Than or Equal Compare Register (QEI1GEC) bits  2011-2020 Microchip Technology Inc. DS70000657J-page 264...
  • Page 265 -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INTTMR[15:0]: Low Word Used to Form 32-Bit Interval Timer Register (INT1TMR) bits  2011-2020 Microchip Technology Inc. DS70000657J-page 265...
  • Page 266 U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 INTHLD[15:0]: Hold Register for Reading and Writing INT1TMRL bits  2011-2020 Microchip Technology Inc. DS70000657J-page 266...
  • Page 267: Serial Peripheral Interface (Spi)

    In 3-pin mode, SSx is not used. In 2-pin mode, neither SDOx nor SSx is used. Figure 18-1 illustrates the block diagram of the SPIx module in Standard and Enhanced modes.  2011-2020 Microchip Technology Inc. DS70000657J-page 267...
  • Page 268 0 SDIx SPIxSR Transfer Transfer 8-Level FIFO 8-Level FIFO Receive Buffer Transmit Buffer SPIxBUF Read SPIxBUF Write SPIxBUF Internal Data Bus Note 1: In Standard mode, the FIFO is only one level deep.  2011-2020 Microchip Technology Inc. DS70000657J-page 268...
  • Page 269 It is always advisable to preload the SPIxBUF Transmit register in advance of the next master transaction cycle. SPIxBUF is transferred to the SPIx Shift register and is empty once the data transmission begins.  2011-2020 Microchip Technology Inc. DS70000657J-page 269...
  • Page 270 001 = Interrupt when data are available in the receive buffer (SRMPT bit is set) 000 = Interrupt when the last data in the receive buffer are read and as a result, the buffer is empty (SRXMPT bit is set)  2011-2020 Microchip Technology Inc. DS70000657J-page 270...
  • Page 271 Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR.  2011-2020 Microchip Technology Inc. DS70000657J-page 271...
  • Page 272 The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1). This bit must be cleared when FRMEN = 1. Do not set both primary and secondary prescalers to the value of 1:1.  2011-2020 Microchip Technology Inc. DS70000657J-page 272...
  • Page 273 The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1). This bit must be cleared when FRMEN = 1. Do not set both primary and secondary prescalers to the value of 1:1.  2011-2020 Microchip Technology Inc. DS70000657J-page 273...
  • Page 274 1 = Frame Sync pulse coincides with first bit clock 0 = Frame Sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced buffer is enabled 0 = Enhanced buffer is disabled (Standard mode)  2011-2020 Microchip Technology Inc. DS70000657J-page 274...
  • Page 275: Inter-Integrated Circuit (I C)

    100 Kbit/second operation. See timing • Intelligent Platform Management Interface (IPMI) specifications, IM10 and IM11, and the Support “Baud Rate Generator” in the “dsPIC33/ PIC24 Family Reference Manual”. • System Management Bus (SMBus) Support  2011-2020 Microchip Technology Inc. DS70000657J-page 275...
  • Page 276 Start and Stop Bit Detect Write Start and Stop I2CxSTAT Bit Generation Read Collision Write Detect I2CxCON Acknowledge Read Generation Clock Stretching Write I2CxTRN Read Shift Clock Reload Control Write BRG Down Counter I2CxBRG Read  2011-2020 Microchip Technology Inc. DS70000657J-page 276...
  • Page 277 In the event you are not able to access the • Webinars product page using the link above, enter this URL in your browser: • All Related “dsPIC33/PIC24 Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en555464 • Development Tools  2011-2020 Microchip Technology Inc. DS70000657J-page 277...
  • Page 278 1 = Enables interrupt when a general call address is received in I2CxRSR (module is enabled for reception) 0 = General call address disabled Note 1: When performing master operations, ensure that the IPMIEN bit is set to ‘0’.  2011-2020 Microchip Technology Inc. DS70000657J-page 278...
  • Page 279 1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of the master Start sequence. 0 = Start condition is not in progress Note 1: When performing master operations, ensure that the IPMIEN bit is set to ‘0’.  2011-2020 Microchip Technology Inc. DS70000657J-page 279...
  • Page 280 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when a Start, Repeated Start or Stop is detected.  2011-2020 Microchip Technology Inc. DS70000657J-page 280...
  • Page 281 1 = Transmit in progress, I2CxTRN is full 0 = Transmit is complete, I2CxTRN is empty Hardware is set when software writes to I2CxTRN. Hardware is clear at completion of a data transmission.  2011-2020 Microchip Technology Inc. DS70000657J-page 281...
  • Page 282 1 = Enables masking for bit Ax + 1 of incoming message address; bit match is not required in this position 0 = Disables masking for bit Ax + 1; bit match is required in this position  2011-2020 Microchip Technology Inc. DS70000657J-page 282...
  • Page 283: Universal Asynchronous Receiver Transmitter (Uart)

    • Loopback mode for Diagnostic Support computers, LIN/J2602, RS-232 and RS-485 interfaces. FIGURE 20-1: UARTx SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator ® IrDA Hardware Flow Control UxRTS/BCLKx UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX  2011-2020 Microchip Technology Inc. DS70000657J-page 283...
  • Page 284 Sleep mode, the baud rate bit Manual” Sections sampling clock, relative to the incoming UxRX • Development Tools bit timing, is no longer synchronized, resulting in the first character being invalid; this is to be expected.  2011-2020 Microchip Technology Inc. DS70000657J-page 284...
  • Page 285 This feature is only available for the 16x BRG mode (BRGH = 0). This feature is only available on 44-pin and 64-pin devices. This feature is only available on 64-pin devices.  2011-2020 Microchip Technology Inc. DS70000657J-page 285...
  • Page 286 This feature is only available for the 16x BRG mode (BRGH = 0). This feature is only available on 44-pin and 64-pin devices. This feature is only available on 64-pin devices.  2011-2020 Microchip Technology Inc. DS70000657J-page 286...
  • Page 287 Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (www.microchip.com/DS70000582) in the “dsPIC33/PIC24 Family Reference Manual” for information on enabling the UARTx module for transmit operation.  2011-2020 Microchip Technology Inc. DS70000657J-page 287...
  • Page 288 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (www.microchip.com/DS70000582) in the “dsPIC33/PIC24 Family Reference Manual” for information on enabling the UARTx module for transmit operation.  2011-2020 Microchip Technology Inc. DS70000657J-page 288...
  • Page 289: Enhanced Can (Ecan™) Module (Dspic33Epxxxgp/Mc50X Devices Only)

    CAN system. The CAN specification is see if it should be received and stored in one of the not covered within this data sheet. The reader can refer receive registers. to the BOSCH CAN specification for further details.  2011-2020 Microchip Technology Inc. DS70000657J-page 289...
  • Page 290 RxF1 Filter TRB1 TX/RX Buffer Control Register RxM1 Mask RxF0 Filter TRB0 TX/RX Buffer Control Register RxM0 Mask Transmit Byte Message Assembly Sequencer Buffer Control Configuration Logic CAN Protocol Engine Interrupts CxTx CxRx  2011-2020 Microchip Technology Inc. DS70000657J-page 290...
  • Page 291 Idle time, which is defined as at • Code Samples least 11 consecutive recessive bits. • Application Notes • Software Libraries • Webinars • All Related “dsPIC33/PIC24 Family Reference Manual” Sections • Development Tools  2011-2020 Microchip Technology Inc. DS70000657J-page 291...
  • Page 292 1 = Enables input capture based on CAN message receive 0 = Disables CAN capture bit 2-1 Unimplemented: Read as ‘0’ bit 0 WIN: SFR Map Window Select bit 1 = Uses filter window 0 = Uses buffer window  2011-2020 Microchip Technology Inc. DS70000657J-page 292...
  • Page 293 10001 = Compares up to Data Byte 3, bit 6 with EID[17] • • • 00001 = Compares up to Data Byte 1, bit 7 with EID[0] 00000 = Does not compare data bytes  2011-2020 Microchip Technology Inc. DS70000657J-page 293...
  • Page 294 0000110 = TRB6 buffer interrupt 0000101 = TRB5 buffer interrupt 0000100 = TRB4 buffer interrupt 0000011 = TRB3 buffer interrupt 0000010 = TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 buffer interrupt  2011-2020 Microchip Technology Inc. DS70000657J-page 294...
  • Page 295 Unimplemented: Read as ‘0’ bit 4-0 FSA[4:0]: FIFO Area Starts with Buffer bits 11111 = Read Buffer RB31 11110 = Read Buffer RB30 • • • 00001 = TX/RX Buffer TRB1 00000 = TX/RX Buffer TRB0  2011-2020 Microchip Technology Inc. DS70000657J-page 295...
  • Page 296 7-6 Unimplemented: Read as ‘0’ bit 5-0 FNRB[5:0]: FIFO Next Read Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer • • • 000001 = TRB1 buffer 000000 = TRB0 buffer  2011-2020 Microchip Technology Inc. DS70000657J-page 296...
  • Page 297 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2011-2020 Microchip Technology Inc. DS70000657J-page 297...
  • Page 298 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 TBIF: TX Buffer Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2011-2020 Microchip Technology Inc. DS70000657J-page 298...
  • Page 299 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 TBIE: TX Buffer Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2011-2020 Microchip Technology Inc. DS70000657J-page 299...
  • Page 300 • • • 00 0010 = T = 2 x 3 x 1/F 00 0001 = T = 2 x 2 x 1/F 00 0000 = T = 2 x 1 x 1/F  2011-2020 Microchip Technology Inc. DS70000657J-page 300...
  • Page 301 • • 000 = Length is 1 x T bit 2-0 PRSEG[2:0]: Propagation Time Segment bits 111 = Length is 8 x T • • • 000 = Length is 1 x T  2011-2020 Microchip Technology Inc. DS70000657J-page 301...
  • Page 302 F2BP[3:0]: RX Buffer Mask for Filter 2 bits (same values as bits[15:12]) bit 7-4 F1BP[3:0]: RX Buffer Mask for Filter 1 bits (same values as bits[15:12]) bit 3-0 F0BP[3:0]: RX Buffer Mask for Filter 0 bits (same values as bits[15:12])  2011-2020 Microchip Technology Inc. DS70000657J-page 302...
  • Page 303 F10BP[3:0]: RX Buffer Mask for Filter 10 bits (same values as bits[15:12]) bit 7-4 F9BP[3:0]: RX Buffer Mask for Filter 9 bits (same values as bits[15:12]) bit 3-0 F8BP[3:0]: RX Buffer Mask for Filter 8 bits (same values as bits[15:12])  2011-2020 Microchip Technology Inc. DS70000657J-page 303...
  • Page 304 F14BP[3:0]: RX Buffer Mask for Filter 14 bits (same values as bits[15:12]) bit 7-4 F13BP[3:0]: RX Buffer Mask for Filter 13 bits (same values as bits[15:12]) bit 3-0 F12BP[3:0]: RX Buffer Mask for Filter 12 bits (same values as bits[15:12])  2011-2020 Microchip Technology Inc. DS70000657J-page 304...
  • Page 305 Unimplemented: Read as ‘0’ bit 1-0 EID[17:16]: Extended Identifier bits 1 = Message address bit, EIDx, must be ‘1’ to match filter 0 = Message address bit, EIDx, must be ‘0’ to match filter  2011-2020 Microchip Technology Inc. DS70000657J-page 305...
  • Page 306 F2MSK[1:0]: Mask Source for Filter 2 bits (same values as bits[15:14]) bit 3-2 F1MSK[1:0]: Mask Source for Filter 1 bits (same values as bits[15:14]) bit 1-0 F0MSK[1:0]: Mask Source for Filter 0 bits (same values as bits[15:14])  2011-2020 Microchip Technology Inc. DS70000657J-page 306...
  • Page 307 F10MSK[1:0]: Mask Source for Filter 10 bits (same values as bits[15:14]) bit 3-2 F9MSK[1:0]: Mask Source for Filter 9 bits (same values as bits[15:14]) bit 1-0 F8MSK[1:0]: Mask Source for Filter 8 bits (same values as bits[15:14])  2011-2020 Microchip Technology Inc. DS70000657J-page 307...
  • Page 308 ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 EID[15:0]: Extended Identifier bits 1 = Includes bit, EIDx, in filter comparison 0 = EIDx bit is a don’t care in filter comparison  2011-2020 Microchip Technology Inc. DS70000657J-page 308...
  • Page 309 ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXFUL[31:16]: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty (cleared by user software)  2011-2020 Microchip Technology Inc. DS70000657J-page 309...
  • Page 310 = Bit is unknown bit 15-0 RXOVF[31:16]: Receive Buffer n Overflow bits 1 = Module attempted to write to a full buffer (set by module) 0 = No overflow condition (cleared by user software)  2011-2020 Microchip Technology Inc. DS70000657J-page 310...
  • Page 311 01 = Low intermediate message priority 00 = Lowest message priority Note 1: This bit is cleared when TXREQ is set. Note: The buffers, SID, EID, DLC, Data Field, and Receive Status registers are located in DMA RAM.  2011-2020 Microchip Technology Inc. DS70000657J-page 311...
  • Page 312 U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 EID[17:6]: Extended Identifier bits  2011-2020 Microchip Technology Inc. DS70000657J-page 312...
  • Page 313 ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 1[15:8]: ECAN Message Byte 1 bits bit 7-0 Byte 0[7:0]: ECAN Message Byte 0 bits  2011-2020 Microchip Technology Inc. DS70000657J-page 313...
  • Page 314 ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Byte 5[15:8]: ECAN Message Byte 5 bits bit 7-0 Byte 4[7:0]: ECAN Message Byte 4 bits  2011-2020 Microchip Technology Inc. DS70000657J-page 314...
  • Page 315 FILHIT[4:0]: Filter Hit Code bits Encodes number of filter that resulted in writing this buffer. bit 7-0 Unimplemented: Read as ‘0’ Note 1: Only written by module for receive buffers, unused for transmit buffers.  2011-2020 Microchip Technology Inc. DS70000657J-page 315...
  • Page 316 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 316...
  • Page 317: Charge Time Measurement Unit (Ctmu)

    CTMUCON1, CTMUCON2 and CTMUICON. CTMUCON1 and CTMUCON2 enable the module and control edge source selection, edge source polarity selection and edge sequencing. The CTMUICON register controls the selection and trim of the current source.  2011-2020 Microchip Technology Inc. DS70000657J-page 317...
  • Page 318 In the event you are not able to access the • Webinars product page using the link above, enter this URL in your browser: • All Related “dsPIC33/PIC24 Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en555464 • Development Tools  2011-2020 Microchip Technology Inc. DS70000657J-page 318...
  • Page 319 The IDISSEN bit, when set to ‘1’, performs this function. The ADC must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array.  2011-2020 Microchip Technology Inc. DS70000657J-page 319...
  • Page 320 EDG2SEL[3:0]: Edge 2 Source Select bits 1111 = Reserved 01xx = Reserved 0100 = CMP1 module 0011 = CTED2 pin 0010 = CTED1 pin 0001 = OC1 module 0000 = IC1 module bit 1-0 Unimplemented: Read as ‘0’  2011-2020 Microchip Technology Inc. DS70000657J-page 320...
  • Page 321 This current range is not available to be used with the internal temperature measurement diode. Refer to the CTMU Current Source Specifications (Table 30-56) in Section 30.0 “Electrical Characteristics” for the current range selection values.  2011-2020 Microchip Technology Inc. DS70000657J-page 321...
  • Page 322 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 322...
  • Page 323: 10-Bit/12-Bit Analog-To-Digital Converter (Adc)

    A block diagram of the ADC module is shown in Figure 23-1. Figure 23-2 provides a diagram of the ADC conversion clock period.  2011-2020 Microchip Technology Inc. DS70000657J-page 323...
  • Page 324 FIGURE 23-1: ADC MODULE BLOCK DIAGRAM WITH CONNECTION OPTIONS FOR ANx PINS AND OP AMPS This diagram depicts all of the available ADC connection options to the four S&H 00000 Channel Scan amplifiers, which are designated: CH0, AN0-ANx CH1, CH2 and CH3. From CTMU CH0SA[4:0] OA1-OA3...
  • Page 325 RC Clock AD1CON3[7:0] ADC Conversion Clock Multiplier 1, 2, 3, 4, 5,..., 256 Note 1: = 1/F See the ADC electrical specifications in Section 30.0 “Electrical Characteristics” for the exact RC clock value.  2011-2020 Microchip Technology Inc. DS70000657J-page 325...
  • Page 326 ADC. As a result, in Manual Sample mode, particularly where the user’s code is set- ting the SAMP bit (AD1CON1[1]), the DONE bit should also be cleared by the user application just before setting the SAMP bit.  2011-2020 Microchip Technology Inc. DS70000657J-page 326...
  • Page 327 Section 24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection. This setting is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. Do not clear the DONE bit in software if auto-sample is enabled (ASAM = 1).  2011-2020 Microchip Technology Inc. DS70000657J-page 327...
  • Page 328 Section 24.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection. This setting is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. Do not clear the DONE bit in software if auto-sample is enabled (ASAM = 1).  2011-2020 Microchip Technology Inc. DS70000657J-page 328...
  • Page 329 11110 = Increments the DMA address after completion of every 31st sample/conversion operation • • • 00001 = Increments the DMA address after completion of every 2nd sample/conversion operation 00000 = Increments the DMA address after completion of every sample/conversion operation  2011-2020 Microchip Technology Inc. DS70000657J-page 329...
  • Page 330 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample MUXA on first sample and Sample MUXB on next sample 0 = Always uses channel input selects for Sample MUXA  2011-2020 Microchip Technology Inc. DS70000657J-page 330...
  • Page 331 • (ADCS[7:0] + 1) = T •1 = T Note 1: This bit is only used if SSRC[2:0] (AD1CON1[7:5]) = 111 and SSRCG (AD1CON1[4]) = 0. This bit is not used if ADRC (AD1CON3[15]) = 1.  2011-2020 Microchip Technology Inc. DS70000657J-page 331...
  • Page 332 010 = Allocates 4 words of buffer to each analog input 001 = Allocates 2 words of buffer to each analog input 000 = Allocates 1 word of buffer to each analog input  2011-2020 Microchip Technology Inc. DS70000657J-page 332...
  • Page 333 Channels 1, 2 and 3. The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON[10]) = 1); otherwise, the ANx input is used.  2011-2020 Microchip Technology Inc. DS70000657J-page 333...
  • Page 334 Channels 1, 2 and 3. The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON[10]) = 1); otherwise, the ANx input is used.  2011-2020 Microchip Technology Inc. DS70000657J-page 334...
  • Page 335 The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON[10]) = 1); otherwise, the ANx input is used. See the “Pin Diagrams” section for the available analog channels for each device.  2011-2020 Microchip Technology Inc. DS70000657J-page 335...
  • Page 336 The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON[10]) = 1); otherwise, the ANx input is used. See the “Pin Diagrams” section for the available analog channels for each device.  2011-2020 Microchip Technology Inc. DS70000657J-page 336...
  • Page 337 All AD1CSSH bits can be selected by user software. However, inputs selected for scan, without a corresponding input on the device, convert V REFL The OAx input is used if the corresponding op amp is selected (OPMODE (CMxCON[10]) = 1); otherwise, the ANx input is used.  2011-2020 Microchip Technology Inc. DS70000657J-page 337...
  • Page 338 For analog inputs that have op amp output function (OAxOUT), op amp output can be accessed for input scan if the corresponding op amp is selected (OPMODE (CMxCON[10[) = 1); otherwise, the ANx input is used.  2011-2020 Microchip Technology Inc. DS70000657J-page 338...
  • Page 339: Peripheral Trigger Generator (Ptg) Module

    The PTG module uses 8-bit commands, called - Op Amp/Comparator “Steps”, that the user writes to the PTG Queue registers (PTGQUE0-PTGQUE7). The registers per- form operations, such as wait for input signal, generate output trigger and wait for timer.  2011-2020 Microchip Technology Inc. DS70000657J-page 339...
  • Page 340 Timer PTGWDTIF PTGQUE0 PTGQUE1 PTGQUE2 PTGQUE3 Command Decoder PTGQUE4 PTGQUE5 PTGQUE6 PTGQUE7 PTGSTEPIF Note 1: This is a dedicated Watchdog Timer for the PTG module and is independent of the device Watchdog Timer.  2011-2020 Microchip Technology Inc. DS70000657J-page 340...
  • Page 341 In the event you are not able to access the • Webinars product page using the link above, enter this URL in your browser: • All Related “dsPIC33/PIC24 Family Reference http://www.microchip.com/wwwproducts/ Manual” Sections Devices.aspx?dDocName=en555464 • Development Tools  2011-2020 Microchip Technology Inc. DS70000657J-page 341...
  • Page 342 These bits apply to the PTGWHI and PTGWLO commands only. This bit is only used with the PTGCTRL Step command software trigger option. Use of the PTG Single-Step mode is reserved for debugging tools only.  2011-2020 Microchip Technology Inc. DS70000657J-page 342...
  • Page 343 These bits apply to the PTGWHI and PTGWLO commands only. This bit is only used with the PTGCTRL Step command software trigger option. Use of the PTG Single-Step mode is reserved for debugging tools only.  2011-2020 Microchip Technology Inc. DS70000657J-page 343...
  • Page 344 011 = Watchdog Timer will time-out after 32 PTG clocks 010 = Watchdog Timer will time-out after 16 PTG clocks 001 = Watchdog Timer will time-out after 8 PTG clocks 000 = Watchdog Timer is disabled  2011-2020 Microchip Technology Inc. DS70000657J-page 344...
  • Page 345 Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1). This register is only used with the PTGCTRL OPTION = 1111 Step command.  2011-2020 Microchip Technology Inc. DS70000657J-page 345...
  • Page 346 Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1). This register is only used with the PTGCTRL OPTION = 1111 Step command.  2011-2020 Microchip Technology Inc. DS70000657J-page 346...
  • Page 347 General Purpose Timer1 Limit register (effective only with a PTGT1 Step command). Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).  2011-2020 Microchip Technology Inc. DS70000657J-page 347...
  • Page 348 May be used to specify the loop count for the PTGJMPC0 Step command or as a limit register for the General Purpose Counter 0. Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).  2011-2020 Microchip Technology Inc. DS70000657J-page 348...
  • Page 349 Holds user-supplied data to be copied to the PTGTxLIM, PTGCxLIM, PTGSDLIM or PTGL0 registers with the PTGCOPY command. Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).  2011-2020 Microchip Technology Inc. DS70000657J-page 349...
  • Page 350 This register holds the 16-bit value to be written to the AD1CHS0 register with the PTGCTRL Step command. Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1).  2011-2020 Microchip Technology Inc. DS70000657J-page 350...
  • Page 351 This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and PTGSTRT = 1). Refer to Table 24-1 for the Step command encoding. The Step registers maintain their values on any type of Reset.  2011-2020 Microchip Technology Inc. DS70000657J-page 351...
  • Page 352 All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction). Refer to Table 24-2 for the trigger output descriptions. This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.  2011-2020 Microchip Technology Inc. DS70000657J-page 352...
  • Page 353 All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction). Refer to Table 24-2 for the trigger output descriptions. This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.  2011-2020 Microchip Technology Inc. DS70000657J-page 353...
  • Page 354 All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction). Refer to Table 24-2 for the trigger output descriptions. This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.  2011-2020 Microchip Technology Inc. DS70000657J-page 354...
  • Page 355 Reserved PTGO27 Reserved PTGO28 Reserved PTGO29 Reserved PTGO30 PTG Output to PPS Input Selection PTGO31 PTG Output to PPS Input Selection Note 1: This feature is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices.  2011-2020 Microchip Technology Inc. DS70000657J-page 355...
  • Page 356 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 356...
  • Page 357: Op Amp/Comparator Module

    CxOUT is not a predefined pin; instead, it must be mapped to a physical pin using Peripheral Pin Select. In order to use the op amp function, OAxOUT/ANx, on the relevant pin, set the corresponding TRISx bit to ‘1’ and the ANSELx bit to ‘1’.  2011-2020 Microchip Technology Inc. DS70000657J-page 357...
  • Page 358 (CVRCON[6]) CVRR REF2O (2) CVR2OE (CVRCON[14]) Note 1: In order to operate with CVRSS = 1, at least one of the comparator modules must be enabled. This reference is (AV + AV )/2.  2011-2020 Microchip Technology Inc. DS70000657J-page 358...
  • Page 359 See the Type C Timer Block Diagram (Figure 13-2). See the Type B Timer Block Diagram (Figure 13-1). See the High-Speed PWMx Module Register Interconnection Diagram (Figure 16-2). See the Oscillator System Diagram (Figure 9-1).  2011-2020 Microchip Technology Inc. DS70000657J-page 359...
  • Page 360 Minimum value for the feedback resistor. Table 30-60 Table 30-61 for the minimum Sample Time (T SAMP or CV are two options that are available for supplying bias voltage to the op amps. REF1O REF2O  2011-2020 Microchip Technology Inc. DS70000657J-page 360...
  • Page 361    Legend: X = Available connection; N/A = Unavailable connection (nominal module input not connected to any device pin); Grayed out cells = Op amp functionality not available for Comparator 4  2011-2020 Microchip Technology Inc. DS70000657J-page 361...
  • Page 362 Minimum value for the feedback resistor. Table 30-60 Table 30-61 for the minimum Sample Time (T SAMP or CV are two options that are available for supplying bias voltage to the op amps. REF1O REF2O  2011-2020 Microchip Technology Inc. DS70000657J-page 362...
  • Page 363 Note 1: Reflects the value of the of the CEVT bit in the respective Op Amp/Comparator Control register, CMxCON[9]. Reflects the value of the COUT bit in the respective Op Amp/Comparator Control register, CMxCON[8].  2011-2020 Microchip Technology Inc. DS70000657J-page 363...
  • Page 364 Note 1: Reflects the value of the of the CEVT bit in the respective Op Amp/Comparator Control register, CMxCON[9]. Reflects the value of the COUT bit in the respective Op Amp/Comparator Control register, CMxCON[8].  2011-2020 Microchip Technology Inc. DS70000657J-page 364...
  • Page 365 Inputs that are selected and not available will be tied to V . See the “Pin Diagrams” section for available inputs for each package. This output is not available when OPMODE (CMxCON[10]) = 1. CM3CON is not available on 28-pin devices.  2011-2020 Microchip Technology Inc. DS70000657J-page 365...
  • Page 366 Inputs that are selected and not available will be tied to V . See the “Pin Diagrams” section for available inputs for each package. This output is not available when OPMODE (CMxCON[10]) = 1. CM3CON is not available on 28-pin devices.  2011-2020 Microchip Technology Inc. DS70000657J-page 366...
  • Page 367 Inputs that are selected and not available will be tied to V . See the “Pin Diagrams” section for available inputs for each package. This input pin is not available in 28-pin devices. Refer to Table 25-1.  2011-2020 Microchip Technology Inc. DS70000657J-page 367...
  • Page 368 Inputs that are selected and not available will be tied to V . See the “Pin Diagrams” section for available inputs for each package. This input pin is not available in 28-pin devices. Refer to Table 25-1.  2011-2020 Microchip Technology Inc. DS70000657J-page 368...
  • Page 369 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = PWM3H 0100 = PWM3L 0011 = PWM2H 0010 = PWM2L 0001 = PWM1H 0000 = PWM1L  2011-2020 Microchip Technology Inc. DS70000657J-page 369...
  • Page 370 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = PWM3H 0100 = PWM3L 0011 = PWM2H 0010 = PWM2L 0001 = PWM1H 0000 = PWM1L  2011-2020 Microchip Technology Inc. DS70000657J-page 370...
  • Page 371 0 = MCI is not connected to AND gate bit 4 ACNEN: AND Gate C Input Inverted Enable bit 1 = Inverted MCI is connected to AND gate 0 = Inverted MCI is not connected to AND gate  2011-2020 Microchip Technology Inc. DS70000657J-page 371...
  • Page 372 0 = MAI is not connected to AND gate bit 0 AANEN: AND Gate A Input Inverted Enable bit 1 = Inverted MAI is connected to AND gate 0 = Inverted MAI is not connected to AND gate  2011-2020 Microchip Technology Inc. DS70000657J-page 372...
  • Page 373 See the Type C Timer Block Diagram (Figure 13-2). See the Type B Timer Block Diagram (Figure 13-1). See the High-Speed PWMx Module Register Interconnection Diagram (Figure 16-2). See the Oscillator System Diagram (Figure 9-1).  2011-2020 Microchip Technology Inc. DS70000657J-page 373...
  • Page 374 The ANSELx register controls the operation of the analog port pins. The port pins that are to function as analog inputs or outputs must have their corresponding ANSELx and TRISx bits set. In order to operate with CVRSS = 1, at least one of the comparator modules must be enabled.  2011-2020 Microchip Technology Inc. DS70000657J-page 374...
  • Page 375: Programmable Cyclic Redundancy Check (Crc) Generator

    CRC BLOCK DIAGRAM CRCDATH CRCDATL Variable FIFO FIFO Empty Event (4x32, 8x16 or 16x8) CRCISEL 2 * F Shift Clock Shift Buffer Set CRCIF LENDIAN Shift Complete Event CRC Shift Engine CRCWDATH CRCWDATL  2011-2020 Microchip Technology Inc. DS70000657J-page 375...
  • Page 376 32, there is no 32nd bit in the “dsPIC33/PIC24 Family Reference Manual” CRCxOR register. • Code Samples • Application Notes • Software Libraries • Webinars • All Related “dsPIC33/PIC24 Family Reference Manual” Sections • Development Tools  2011-2020 Microchip Technology Inc. DS70000657J-page 376...
  • Page 377 1 = Data word is shifted into the CRC starting with the LSb (little-endian) 0 = Data word is shifted into the CRC starting with the MSb (big-endian) bit 2-0 Unimplemented: Read as ‘0’  2011-2020 Microchip Technology Inc. DS70000657J-page 377...
  • Page 378 These bits set the width of the data word (DWIDTH[4:0] + 1). bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 PLEN[4:0]: Polynomial Length Select bits These bits set the length of the polynomial (Polynomial Length = PLEN[4:0] + 1).  2011-2020 Microchip Technology Inc. DS70000657J-page 378...
  • Page 379 -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 X[15:1]: XOR of Polynomial Term X Enable bits bit 0 Unimplemented: Read as ‘0’  2011-2020 Microchip Technology Inc. DS70000657J-page 379...
  • Page 380 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 380...
  • Page 381: Special Features

    Flash Configuration bytes, enabling code protection as a result. Therefore, users should avoid performing page erase operations on the last page of program memory. The Configuration Flash bytes map is shown in Table 27-1.  2011-2020 Microchip Technology Inc. DS70000657J-page 381...
  • Page 382 — = unimplemented, read as ‘1’. Note 1: This bit is only available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. This bit is reserved and must be programmed as ‘0’. These bits are reserved and must be programmed as ‘1’.  2011-2020 Microchip Technology Inc. DS70000657J-page 382...
  • Page 383 When JTAGEN = 1, an internal pull-up resistor is enabled on the TMS pin. Erased devices default to JTAGEN = 1. Applications requiring I/O pins in a high-impedance state (tri-state) in Reset should use pins other than TMS for this purpose.  2011-2020 Microchip Technology Inc. DS70000657J-page 383...
  • Page 384 When JTAGEN = 1, an internal pull-up resistor is enabled on the TMS pin. Erased devices default to JTAGEN = 1. Applications requiring I/O pins in a high-impedance state (tri-state) in Reset should use pins other than TMS for this purpose.  2011-2020 Microchip Technology Inc. DS70000657J-page 384...
  • Page 385 1 = General Segment has no security 0 = General Segment has high security bit 0 GWRP: General Segment Program Flash Write Protection bit 1 = General Segment is not write-protected 0 = General Segment is write-protected  2011-2020 Microchip Technology Inc. DS70000657J-page 385...
  • Page 386 ICS[1:0]: ICD Communication Channel Select bits 11 = Communicates on PGEC1 and PGED1 10 = Communicates on PGEC2 and PGED2 01 = Communicates on PGEC3 and PGED3 00 = Reserved, do not use  2011-2020 Microchip Technology Inc. DS70000657J-page 386...
  • Page 387 POSCMD[1:0]: Primary Oscillator Configuration bits 11 = Primary Oscillator is disabled 10 = HS Oscillator mode selected (10 MHz-40 MHz) 01 = MS Oscillator mode selected (3.5 MHz-10 MHz) 00 = External Clock mode selected  2011-2020 Microchip Technology Inc. DS70000657J-page 387...
  • Page 388 011 = Primary Oscillator with PLL module (MS+PLL, HS+PLL, EC+PLL) 010 = Primary Oscillator (MS, HS, EC) 001 = Fast RC Oscillator with Divide-by-N with PLL module (FRCDIV+PLL) 000 = Fast RC (FRC) Oscillator  2011-2020 Microchip Technology Inc. DS70000657J-page 388...
  • Page 389 ALTI2C1: Alternate I2C1 Pin Mapping bit 1 = Default location for SCL1/SDA1 pins 0 = Alternate location for SCL1/SDA1 pins (ASCL1/ASDA1) bit 3 Reserved: Read as ‘1’ bit 2-0 Unused: Reads contents of Flash Configuration Words  2011-2020 Microchip Technology Inc. DS70000657J-page 389...
  • Page 390 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1  2011-2020 Microchip Technology Inc. DS70000657J-page 390...
  • Page 391 U = Unimplemented bit bit 23-0 DEVREV[23:0]: Device Revision bits Note 1: Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration Bits” (DS70663) for the list of device revision values.  2011-2020 Microchip Technology Inc. DS70000657J-page 391...
  • Page 392 The BOR status bit (RCON[1]) is set to indicate that a BOR has occurred. The BOR circuit continues to oper- ate while in Sleep or Idle modes and resets the device should V fall below the BOR threshold voltage.  2011-2020 Microchip Technology Inc. DS70000657J-page 392...
  • Page 393 Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle WDTPOST[3:0] WDTPRE SWDTEN Wake-up FWDTEN Prescaler Postscaler LPRC Clock (Divide-by-N1) (Divide-by-N2) Reset WINDIS WDT Window Select WDTWIN[1:0] CLRWDT Instruction  2011-2020 Microchip Technology Inc. DS70000657J-page 393...
  • Page 394 Note: Refer “CodeGuard™ Security” (www.microchip.com/DS70634) • PGEC1 and PGED1 “dsPIC33/PIC24 Family Reference • PGEC2 and PGED2 Manual” for further information on usage, • PGEC3 and PGED3 configuration operation CodeGuard Security.  2011-2020 Microchip Technology Inc. DS70000657J-page 394...
  • Page 395: Instruction Set Summary

    However, word or byte-oriented file register instructions have two operands: • The file register specified by the value ‘f’ • The destination, which could be either the file register ‘f’ or the W0 register, which is denoted as ‘WREG’  2011-2020 Microchip Technology Inc. DS70000657J-page 395...
  • Page 396 6-bit signed literal {-16...16} Slit6 Base W register {W0...W15} Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }  2011-2020 Microchip Technology Inc. DS70000657J-page 396...
  • Page 397 [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Y Data Space Prefetch Destination register for DSP instructions {W4...W7}  2011-2020 Microchip Technology Inc. DS70000657J-page 397...
  • Page 398 Write Z bit to Ws[Wb] None BSW.Z Ws,Wb Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.  2011-2020 Microchip Technology Inc. DS70000657J-page 398...
  • Page 399 None CPBNE CPBNE Wb,Wn,Expr Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.  2011-2020 Microchip Technology Inc. DS70000657J-page 399...
  • Page 400 Square and Accumulate OA,OB,OAB, Wm*Wm,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.  2011-2020 Microchip Technology Inc. DS70000657J-page 400...
  • Page 401 W3:W2 = f * WREG None Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.  2011-2020 Microchip Technology Inc. DS70000657J-page 401...
  • Page 402 OA,OB,OAB, SFTAC Acc,#Slit6 SA,SB,SAB Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.  2011-2020 Microchip Technology Inc. DS70000657J-page 402...
  • Page 403 Wnd = Zero-Extend Ws C,Z,N Ws,Wnd Note 1: These instructions are available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only. Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.  2011-2020 Microchip Technology Inc. DS70000657J-page 403...
  • Page 404 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 404...
  • Page 405: Development Support

    DSCs. MPLAB X tools are compatible ® ® ® with Windows , Linux and Mac operating systems while Atmel Studio tools are compatible with Windows. Go to the following website for more information and details: https://www.microchip.com/development-tools/  2011-2020 Microchip Technology Inc. DS70000657J-page 405...
  • Page 406 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 406...
  • Page 407: Electrical Characteristics

    2: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2). 3: See the “Pin Diagrams” section for the 5V tolerant pins. 4: Exceptions are: dsPIC33EPXXXGP502, dsPIC33EPXXXMC202/502 and PIC24EPXXXGP/MC202 devices, which have a maximum sink/source capability of 130 mA.  2011-2020 Microchip Technology Inc. DS70000657J-page 407...
  • Page 408 Package Thermal Resistance, 28-Pin SOIC 69.7 — °C/W  Package Thermal Resistance, 28-Pin SPDIP 60.0 — °C/W Note 1: Junction to ambient thermal resistance, Theta- ( ) numbers are achieved by package simulations.  2011-2020 Microchip Technology Inc. DS70000657J-page 408...
  • Page 409 Typ. Max. Units Comments External Filter Capacitor — µF Capacitor must have a low Value series resistance (< 1 Ohm)  V Note 1: Typical V voltage = 1.8 volts when V DDMIN  2011-2020 Microchip Technology Inc. DS70000657J-page 409...
  • Page 410 • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating or being clocked (defined PMDx bits are all ‘1’s) • NOP instructions are executed in while(1) loop • JTAG is disabled  2011-2020 Microchip Technology Inc. DS70000657J-page 410...
  • Page 411 • The NVMSIDL bit (NVMCON[12]) = 1 (i.e., Flash regulator is set to standby while the device is in Idle mode) • The VREGSF bit (RCON[11]) = 0 (i.e., Flash regulator is set to standby while the device is in Sleep mode) • JTAG is disabled  2011-2020 Microchip Technology Inc. DS70000657J-page 411...
  • Page 412 • The VREGS bit (RCON[8]) = 0 (i.e., core regulator is set to standby while the device is in Sleep mode) • The VREGSF bit (RCON[11]) = 0 (i.e., Flash regulator is set to standby while the device is in Sleep mode) • JTAG is disabled  2011-2020 Microchip Technology Inc. DS70000657J-page 412...
  • Page 413 • No peripheral modules are operating; however, every peripheral is being clocked (all PMDx bits are zeroed) • CPU is executing while(1) statement • JTAG is disabled Parameter is characterized but not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 413...
  • Page 414 Any number and/or combination of I/O pins not excluded under I or I conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested.  2011-2020 Microchip Technology Inc. DS70000657J-page 414...
  • Page 415 Any number and/or combination of I/O pins not excluded under I or I conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested.  2011-2020 Microchip Technology Inc. DS70000657J-page 415...
  • Page 416 Any number and/or combination of I/O pins not excluded under I or I conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested.  2011-2020 Microchip Technology Inc. DS70000657J-page 416...
  • Page 417 Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Parameters are for design guidance only and are not tested in manufacturing. The V specification is relative to V  2011-2020 Microchip Technology Inc. DS70000657J-page 417...
  • Page 418 = +85°C cycles D138b Word Write Cycle Time — — = +125°C cycles Note 1: Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameter characterized but not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 418...
  • Page 419 In XT and HS modes, when OSCO external clock is used to drive OSC1 DO56 All I/O Pins and OSC2 — — EC mode DO58 SCLx, SDAx — — In I C mode  2011-2020 Microchip Technology Inc. DS70000657J-page 419...
  • Page 420 “Maximum” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. This parameter is characterized, but not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 420...
  • Page 421 LPRC — = 3.0-3.6V -10°C  T  +85°C — = 3.0-3.6V +85°C  T  +125°C V F21b LPRC — = 3.0-3.6V Note 1: The change of LPRC frequency as V changes.  2011-2020 Microchip Technology Inc. DS70000657J-page 421...
  • Page 422 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. FIGURE 30-4: BOR AND MASTER CLEAR RESET TIMING CHARACTERISTICS MCLR MCLR (SY20) Various Delays (depending on configuration) (SY30) Reset Sequence CPU Starts Fetching Code  2011-2020 Microchip Technology Inc. DS70000657J-page 422...
  • Page 423 OSCDFRC Delay SY38 LPRC Oscillator Start-up — — µs OSCDLPRC Delay Note 1: These parameters are characterized but not tested in manufacturing. Data in “Typical” column are at 3.3V, +25°C unless otherwise stated.  2011-2020 Microchip Technology Inc. DS70000657J-page 423...
  • Page 424 Delay from External T1CK 0.75 T + 40 — 1.75 T + 40 CKEXTMRL Clock Edge to Timer Increment Note 1: Timer1 is a Type A. These parameters are characterized, but are not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 424...
  • Page 425 (1, 8, 64, 256) TC20 Delay from External TxCK 0.75 T + 40 — 1.75 T + 40 CKEXTMRL Clock Edge to Timer Increment Note 1: These parameters are characterized, but are not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 425...
  • Page 426 (1, 4, 16) (0.5 T /N) + 25 IC15 ICx Input Period Greater of — 25 + 50 or (1 T /N) + 50 Note 1: These parameters are characterized, but not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 426...
  • Page 427 Units Conditions OC15 Fault Input to PWMx I/O — — + 20 Change OC20 Fault Input Pulse Width + 20 — — Note 1: These parameters are characterized but not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 427...
  • Page 428 — See Parameter DO31 RPWM Fault Input  to PWMx MP20 — — I/O Change MP30 Fault Input Pulse Width — — Note 1: These parameters are characterized but not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 428...
  • Page 429 — Period with prescaler (1 T /N) + 50 TQ20 Delay from External TQCK — — CKEXTMRL Clock Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 429...
  • Page 430 N = Index Channel Digital Filter Clock Divide Select bits. Refer to “Quadrature Encoder Interface (QEI)” (www.microchip.com/DS70000601) in the “dsPIC33/PIC24 Family Reference Manual”. Please see the Microchip website for the latest family reference manual sections.  2011-2020 Microchip Technology Inc. DS70000657J-page 430...
  • Page 431 Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but index pulse recognition occurs on the falling edge.  2011-2020 Microchip Technology Inc. DS70000657J-page 431...
  • Page 432 (CKP = 0) SP10 SP21 SP20 SCK2 (CKP = 1) SP35 SP20 SP21 SDO2 Bit 14 - - - - - -1 SP30, SP31 SP30, SP31 Note: Refer to Figure 30-1 for load conditions.  2011-2020 Microchip Technology Inc. DS70000657J-page 432...
  • Page 433 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK2 is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPI2 pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 433...
  • Page 434 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK2 is 111 ns. The clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPI2 pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 434...
  • Page 435 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK2 is 111 ns. The clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPI2 pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 435...
  • Page 436 SDO2 Bit 14 - - - - - -1 SP30, SP31 SP51 SDI2 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 30-1 for load conditions.  2011-2020 Microchip Technology Inc. DS70000657J-page 436...
  • Page 437 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK2 is 66.7 ns. Therefore, the SCK2 clock generated by the master must not violate this specification. Assumes 50 pF load on all SPI2 pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 437...
  • Page 438 SDO2 Bit 14 - - - - - -1 SP30, SP31 SP51 SDI2 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 30-1 for load conditions.  2011-2020 Microchip Technology Inc. DS70000657J-page 438...
  • Page 439 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK2 is 91 ns. Therefore, the SCK2 clock generated by the master must not violate this specification. Assumes 50 pF load on all SPI2 pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 439...
  • Page 440 SDO2 Bit 14 - - - - - -1 SP30, SP31 SP51 SDI2 Bit 14 - - - -1 MSb In LSb In SP41 SP40 Note: Refer to Figure 30-1 for load conditions.  2011-2020 Microchip Technology Inc. DS70000657J-page 440...
  • Page 441 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK2 is 66.7 ns. Therefore, the SCK2 clock generated by the master must not violate this specification. Assumes 50 pF load on all SPI2 pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 441...
  • Page 442 SDO2 Bit 14 - - - - - -1 SP30, SP31 SP51 SDI2 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 30-1 for load conditions.  2011-2020 Microchip Technology Inc. DS70000657J-page 442...
  • Page 443 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK2 is 91 ns. Therefore, the SCK2 clock generated by the master must not violate this specification. Assumes 50 pF load on all SPI2 pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 443...
  • Page 444 (CKP = 0) SP10 SP21 SP20 SCK1 (CKP = 1) SP35 SP20 SP21 Bit 14 - - - - - -1 SDO1 SP30, SP31 SP30, SP31 Note: Refer to Figure 30-1 for load conditions.  2011-2020 Microchip Technology Inc. DS70000657J-page 444...
  • Page 445 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK1 is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPI1 pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 445...
  • Page 446 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK1 is 100 ns. The clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPI1 pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 446...
  • Page 447 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK1 is 100 ns. The clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPI1 pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 447...
  • Page 448 SDO1 Bit 14 - - - - - -1 SP30, SP31 SP51 SDI1 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 30-1 for load conditions.  2011-2020 Microchip Technology Inc. DS70000657J-page 448...
  • Page 449 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must not violate this specification. Assumes 50 pF load on all SPI1 pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 449...
  • Page 450 Bit 14 - - - - - -1 SDO1 SP30, SP31 SP51 SDI1 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 30-1 for load conditions.  2011-2020 Microchip Technology Inc. DS70000657J-page 450...
  • Page 451 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK1 is 91 ns. Therefore, the SCK1 clock generated by the master must not violate this specification. Assumes 50 pF load on all SPI1 pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 451...
  • Page 452 SDO1 Bit 14 - - - - - -1 SP30, SP31 SP51 SDI1 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 30-1 for load conditions.  2011-2020 Microchip Technology Inc. DS70000657J-page 452...
  • Page 453 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must not violate this specification. Assumes 50 pF load on all SPI1 pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 453...
  • Page 454 SDO1 Bit 14 - - - - - -1 SP30, SP31 SP51 SDI1 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 30-1 for load conditions.  2011-2020 Microchip Technology Inc. DS70000657J-page 454...
  • Page 455 Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. The minimum clock period for SCK1 is 91 ns. Therefore, the SCK1 clock generated by the master must not violate this specification. Assumes 50 pF load on all SPI1 pins.  2011-2020 Microchip Technology Inc. DS70000657J-page 455...
  • Page 456 FIGURE 30-31: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM11 IM20 IM21 IM10 SCLx IM26 IM11 IM33 IM25 IM10 SDAx IM40 IM40 IM45 SDAx Note: Refer to Figure 30-1 for load conditions.  2011-2020 Microchip Technology Inc. DS70000657J-page 456...
  • Page 457 Microchip website for the latest family reference manual sections. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). Typical value for this parameter is 130 ns. These parameters are characterized, but not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 457...
  • Page 458 IS31 IS34 IS30 IS33 SDAx Stop Start Condition Condition FIGURE 30-33: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS26 IS30 IS25 IS33 IS31 SDAx IS40 IS40 IS45 SDAx  2011-2020 Microchip Technology Inc. DS70000657J-page 458...
  • Page 459 Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). Typical value for this parameter is 130 ns. These parameters are characterized, but not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 459...
  • Page 460 UARTx Wake-up Note 1: These parameters are characterized but not tested in manufacturing. Data in “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2011-2020 Microchip Technology Inc. DS70000657J-page 460...
  • Page 461 These parameters have a combined effect on the actual performance of the comparator. Input resistance (R1) must be less than or equal to 2 kOhm. The resulting minimum gain of the op amp circuit is equal to four.  2011-2020 Microchip Technology Inc. DS70000657J-page 461...
  • Page 462 These parameters have a combined effect on the actual performance of the comparator. Input resistance (R1) must be less than or equal to 2 kOhm. The resulting minimum gain of the op amp circuit is equal to four.  2011-2020 Microchip Technology Inc. DS70000657J-page 462...
  • Page 463 Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 Table 30-13 for the minimum and maximum BOR values. Parameter is characterized but not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 463...
  • Page 464 • ADC module configured for conversion speed of 500 ksps • All PMDx bits are cleared (PMDx = 0) • Executing a while(1) statement • Device operating from the FRC with no PLL  2011-2020 Microchip Technology Inc. DS70000657J-page 464...
  • Page 465 Analog modules (ADC, op amp/comparator and comparator voltage reference) may have degraded performance. Refer to Parameter BO10 Table 30-13 for the minimum and maximum BOR values. Parameter is characterized but not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 465...
  • Page 466 BO10 Table 30-13 for the minimum and maximum BOR values. For all accuracy specifications, V = AV = 0V and AV = 3.6V. REFL REFH Parameters are characterized but not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 466...
  • Page 467 BO10 Table 30-13 for the minimum and maximum BOR values. For all accuracy specifications, V = AV = 0V and AV = 3.6V. REFL REFH Parameters are characterized but not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 467...
  • Page 468 “dsPIC33/PIC24 Family Reference Manual”. 8 – Convert bit 0. 3 – Software clears AD1CON1. SAMP to start conversion. 9 – One T for end of conversion. 4 – Sampling ends, conversion sequence starts.  2011-2020 Microchip Technology Inc. DS70000657J-page 468...
  • Page 469 , is the time required for the ADC module to stabilize at the appropriate level when the module is turned on (ADON (AD1CON1[15]) = 1). During this time, the ADC result is indeterminate.  2011-2020 Microchip Technology Inc. DS70000657J-page 469...
  • Page 470 “Analog-to-Digital Converter (ADC)” (DS70621) 7 – Begin conversion of next channel. in the “dsPIC33/PIC24 Family Reference Manual”. 3 – Convert bit 9. 8 – Sample for time specified by SAMC[4:0]. 4 – Convert bit 8.  2011-2020 Microchip Technology Inc. DS70000657J-page 470...
  • Page 471 DMA Byte/Word Transfer Latency — — Note 1: These parameters are characterized, but not tested in manufacturing. Because DMA transfers use the CPU data bus, this time is dependent on other functions on the bus.  2011-2020 Microchip Technology Inc. DS70000657J-page 471...
  • Page 472 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 472...
  • Page 473: High-Temperature Electrical Characteristics

    2: AEC-Q100 reliability testing for devices intended to operate at +150°C is 1,000 hours. Any design in which the total operating time from +125°C to +150°C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc. 3: Refer to the “Pin...
  • Page 474 DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) -40°C  T  +150°C Operating temperature Parameter Symbol Characteristic Units Conditions Operating Voltage HDC10 Supply Voltage — -40°C to +150°C  2011-2020 Microchip Technology Inc. DS70000657J-page 474...
  • Page 475 Typical Units Conditions Ratio HDC72a HDC72f — 1:64 +150°C 3.3V 40 MIPS HDC72g — 1:128 Note 1: Parameters with Doze ratios of 1:64 and 1:128 are characterized, but are not tested in manufacturing.  2011-2020 Microchip Technology Inc. DS70000657J-page 475...
  • Page 476 1000 E/W cycles or less and no RETD other specifications are violated Note 1: These parameters are assured by design, but are not characterized or tested in manufacturing. Programming of the Flash memory is allowed up to +150°C.  2011-2020 Microchip Technology Inc. DS70000657J-page 476...
  • Page 477 = 32 MHz, D = 5%, SPIx bit rate clock (i.e., SCKx) is 2 MHz. SPI SCK Jitter ----------------------------- - --------- - ------- - 1.25% 32 MHz   ------------------- -   2 MHz  2011-2020 Microchip Technology Inc. DS70000657J-page 477...
  • Page 478 Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) -40°C  T  +150°C Operating temperature Param Symbol Characteristic Min. Typ. Max. Units Conditions Op Amp DC Characteristics HCM42 Op Amp Offset Voltage ±5 OFFSET  2011-2020 Microchip Technology Inc. DS70000657J-page 478...
  • Page 479 These parameters are characterized, but are tested at 20 ksps only. These parameters are characterized by similarity, but are not tested in manufacturing. Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.  2011-2020 Microchip Technology Inc. DS70000657J-page 479...
  • Page 480 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 480...
  • Page 481: Dc And Ac Device Characteristics Graphs

    32.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
  • Page 482 FIGURE 32-5: TYPICAL I CURRENT @ V = 3.3V FIGURE 32-7: TYPICAL I CURRENT @ V = 3.3V DOZE 800.00 800.00 45.00 45.00 700.00 700.00 40.00 40.00 600.00 600.00 35.00 35.00 30.00 30.00 500.00 500.00 25.00 25.00 400.00 400.00 20.00 20.00 300.00 300.00...
  • Page 483 FIGURE 32-9: TYPICAL FRC FREQUENCY @ V = 3.3V FIGURE 32-11: TYPICAL CTMU TEMPERATURE DIODE FORWARD VOLTAGE 7380 7380 0.850 0.850 7370 7370 0.800 0.800 7360 7360 0.750 0.750 = 0.721 7350 7350 0.700 0.700 7340 7340 0.650 0.650 = 0.658 7330 7330 0.600...
  • Page 484 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 484...
  • Page 485: Packaging Information

    In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2011-2020 Microchip Technology Inc. DS70000657J-page 485...
  • Page 486 44-Lead VTLA (TLA) Example 33EP64GP XXXXXXXXXX 504-I/TL XXXXXXXXXX XXXXXXXXXX 1310017 YYWWNNN 44-Lead TQFP Example XXXXXXXXXX 33EP64GP XXXXXXXXXX 504-I/PT XXXXXXXXXX 1310017 YYWWNNN 44-Lead QFN (8x8x0.9 mm) Example XXXXXXXXXXX 33EP64GP XXXXXXXXXXX 504-I/ML XXXXXXXXXXX 1310017 YYWWNNN  2011-2020 Microchip Technology Inc. DS70000657J-page 486...
  • Page 487 XXXXXXXXXXX 33EP64GP XXXXXXXXXXX 504-I/MV XXXXXXXXXXX 1310017 YYWWNNN 64-Lead QFN (9x9x0.9 mm) Example XXXXXXXXXXX dsPIC33EP XXXXXXXXXXX 64GP506 XXXXXXXXXXX -I/MR YYWWNNN 1310017 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX dsPIC33EP XXXXXXXXXX 64GP506 XXXXXXXXXX -I/PT 1310017 YYWWNNN  2011-2020 Microchip Technology Inc. DS70000657J-page 487...
  • Page 488  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%  2011-2020 Microchip Technology Inc. DS70000657J-page 488...
  • Page 489 AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2020 Microchip Technology Inc. DS70000657J-page 489...
  • Page 490 AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2020 Microchip Technology Inc. DS70000657J-page 490...
  • Page 491 AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2020 Microchip Technology Inc. DS70000657J-page 491...
  • Page 492 AND PIC24EPXXXGP/MC20X  2011-2020 Microchip Technology Inc. DS70000657J-page 492...
  • Page 493 AND PIC24EPXXXGP/MC20X Notes:  2011-2020 Microchip Technology Inc. DS70000657J-page 493...
  • Page 494 AND PIC24EPXXXGP/MC20X  2011-2020 Microchip Technology Inc. DS70000657J-page 494...
  • Page 495 AND PIC24EPXXXGP/MC20X  2011-2020 Microchip Technology Inc. DS70000657J-page 495...
  • Page 496 AND PIC24EPXXXGP/MC20X  2011-2020 Microchip Technology Inc. DS70000657J-page 496...
  • Page 497 /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 00 ± [[ PP %RG\ >4)16@ ZLWK  PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ  2011-2020 Microchip Technology Inc. DS70000657J-page 497...
  • Page 498 0.10 C A B SEATING PLANE SIDE VIEW 0.10 C A B NOTE 1 16X b 0..07 C A B 0.05 BOTTOM VIEW Microchip Technology Drawing C04-436–M5 Rev B Sheet 1 of 2  2011-2020 Microchip Technology Inc. DS70000657J-page 498...
  • Page 499 Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-436–M5 Rev B Sheet 2 of 2  2011-2020 Microchip Technology Inc. DS70000657J-page 499...
  • Page 500 BSC: Basic Dimension. Theoretically exact value shown without tolerances. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2436–M5 Rev B  2011-2020 Microchip Technology Inc. DS70000657J-page 500...
  • Page 501 AND PIC24EPXXXGP/MC20X  2011-2020 Microchip Technology Inc. DS70000657J-page 501...
  • Page 502 AND PIC24EPXXXGP/MC20X  2011-2020 Microchip Technology Inc. DS70000657J-page 502...
  • Page 503 AND PIC24EPXXXGP/MC20X  2011-2020 Microchip Technology Inc. DS70000657J-page 503...
  • Page 504 0.10 C SEATING PLANE 0.08 C SIDE VIEW 0.10 C A B 0.10 DETAIL A (NE-1) X e 44X K (ND-1) X e BOTTOM VIEW Microchip Technology Drawing C04-157D Sheet 1 of 2  2011-2020 Microchip Technology Inc. DS70000657J-page 504...
  • Page 505 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-157D Sheet 2 of 2  2011-2020 Microchip Technology Inc. DS70000657J-page 505...
  • Page 506 AND PIC24EPXXXGP/MC20X  2011-2020 Microchip Technology Inc. DS70000657J-page 506...
  • Page 507 TOP VIEW 0.20 C A B SEATING PLANE 0.10 C SIDE VIEW 1 2 3 NOTE 1 44 X b 0.20 C A B BOTTOM VIEW Microchip Technology Drawing C04-076C Sheet 1 of 2  2011-2020 Microchip Technology Inc. DS70000657J-page 507...
  • Page 508 Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076C Sheet 2 of 2  2011-2020 Microchip Technology Inc. DS70000657J-page 508...
  • Page 509 Contact Pad Width (X44) 0.55 Contact Pad Length (X44) 1.50 Distance Between Pads 0.25 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2076B  2011-2020 Microchip Technology Inc. DS70000657J-page 509...
  • Page 510 SEATING PLANE 0.08 C SIDE VIEW 0.10 C A B 0.10 C A B NOTE 1 44X b 0.07 C A B 0.05 BOTTOM VIEW Microchip Technology Drawing C04-103D Sheet 1 of 2  2011-2020 Microchip Technology Inc. DS70000657J-page 510...
  • Page 511 Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-103D Sheet 2 of 2  2011-2020 Microchip Technology Inc. DS70000657J-page 511...
  • Page 512 BSC: Basic Dimension. Theoretically exact value shown without tolerances. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing No. C04-2103C  2011-2020 Microchip Technology Inc. DS70000657J-page 512...
  • Page 513 AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2020 Microchip Technology Inc. DS70000657J-page 513...
  • Page 514 AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2020 Microchip Technology Inc. DS70000657J-page 514...
  • Page 515 AND PIC24EPXXXGP/MC20X  2011-2020 Microchip Technology Inc. DS70000657J-page 515...
  • Page 516 AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2020 Microchip Technology Inc. DS70000657J-page 516...
  • Page 517 AND PIC24EPXXXGP/MC20X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2020 Microchip Technology Inc. DS70000657J-page 517...
  • Page 518 0.20 C A-B D NOTE 1 0.20 H A-B D TOP VIEW 0.05 SEATING PLANE 64 X b 0.08 C 0.08 C A-B D SIDE VIEW Microchip Technology Drawing C04-085C Sheet 1 of 2  2011-2020 Microchip Technology Inc. DS70000657J-page 518...
  • Page 519 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-085C Sheet 2 of 2  2011-2020 Microchip Technology Inc. DS70000657J-page 519...
  • Page 520 Contact Pad Length (X28) 1.50 Distance Between Pads 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2085B Sheet 1 of 1  2011-2020 Microchip Technology Inc. DS70000657J-page 520...
  • Page 521: Appendix A: Revision History

    Updated the bit definitions for the IRNG[1:0] bits in the CTMU Current Control Measurement Unit (CTMU)” Register (see Register 22-3). Section 25.0 “Op amp/ Updated the voltage reference block diagrams (see Figure 25-1 and Figure 25-2). Comparator Module”  2011-2020 Microchip Technology Inc. DS70000657J-page 521...
  • Page 522 CTMUI4, CTMUFV1, and CTMUFV2 to the CTMU Current Source Specifications (see Table 30-55). Section 31.0 “Packaging Updated packages by replacing references of VLAP with TLA. Information” “Product Identification Changed VLAP to TLA. System”  2011-2020 Microchip Technology Inc. DS70000657J-page 522...
  • Page 523 Updated the bit values for the OCx clock source of the OCTSEL[2:0] bits in the Compare” OCxCON1 register (see Register 15-1). Removed the DCB[1:0] bits from the Output Compare x Control Register 2 (see Register 15-2).  2011-2020 Microchip Technology Inc. DS70000657J-page 523...
  • Page 524 Updated the Minimum, Typical, and Maximum values for Parameter SY37 in the Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements (see Table 30-24). The Maximum Data Rate values were updated for the SPI2 Maximum Data/Clock Rate Summary (see Table 30-35)  2011-2020 Microchip Technology Inc. DS70000657J-page 524...
  • Page 525 ADC Module Specifications (see Table 30-58). Updated Note 2 in the ADC Conversion (12-bit Mode) Timing Requirements (see Table 30-59). Updated Note 1 in the ADC Conversion (10-bit Mode) Timing Requirements (see Table 30-60).  2011-2020 Microchip Technology Inc. DS70000657J-page 525...
  • Page 526 • Table 30-1 • Table 30-4 • Table 30-12 • Table 30-14 • Table 30-15 • Table 30-16 • Table 30-56 • Table 30-57 • Table 30-58 • Table 30-59 • Table 30-60  2011-2020 Microchip Technology Inc. DS70000657J-page 526...
  • Page 527 Added Power-Down Current (Ipd) parameters for the new 512-Kbyte devices (see Table 30-8). Updated the Minimum value for Parameter CM34 (see Table 30-53). Updated the Minimum and Maximum values and the Conditions for paramteer SY12 (see Table 30-22).  2011-2020 Microchip Technology Inc. DS70000657J-page 527...
  • Page 528 • Corrects reference description in xxxxx (now (AV )/2) • Changes CMSTAT[15] in Register 25-1 to “PSIDL” Section 27.0 “Special • Corrects the addresses of all Configuration bytes for 512 Kbyte devices Features”  2011-2020 Microchip Technology Inc. DS70000657J-page 528...
  • Page 529 Device Characteristics curves for the different program memory sizes Graphs” Section 33.0 “Packaging • Replaces drawing C04-149C (64-pin QFN, 7.15 x 7.15 exposed pad) with C04-154A Information” (64-pin QFN, 5.4 x 5.4 exposed pad)  2011-2020 Microchip Technology Inc. DS70000657J-page 529...
  • Page 530 • Corrects 512K part power-down currents based on test data Section 30.0 “Electrical Characteristics” • Corrects WDT timing limits based on LPRC oscillator tolerance Section 31.0 “High- • Adds Table 31-5 (DC Characteristics: Idle Current (I IDLE Temperature Electrical Characteristics”  2011-2020 Microchip Technology Inc. DS70000657J-page 530...
  • Page 531 Characteristics Graphs” Section 33.0 “Packaging • Adds package marking diagram in Section 33.1 “Package Marking Information”. Information” • Adds packaging diagrams to Section 33.2 “Package Details”. “Product Identification System” • Adds M5 packaging description.  2011-2020 Microchip Technology Inc. DS70000657J-page 531...
  • Page 532 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 532...
  • Page 533: Index

    SPI2 Slave Mode (Full-Duplex, CKE = 1, Shared Port Structure..........175 CKP = 1, SMP = 0) Requirements ....439 Single-Phase Synchronous Buck Converter ....35 Timer1 External Clock Requirements ....... 424 SPIx Module ............. 268  2011-2020 Microchip Technology Inc. DS70000657J-page 533...
  • Page 534 Devices ............... 62 Modes of Operation ..........291 Memory Map for PIC24EP32GP/MC20X/50X Overview..............289 Devices ............... 59 Resources ..............291 Memory Map for PIC24EP512GP/MC20X/50X Electrical Characteristics ..........407 Devices ............... 63 AC..............419, 477  2011-2020 Microchip Technology Inc. DS70000657J-page 534...
  • Page 535 Selectable Input Sources.......... 179 Summary..............395 Peripheral Trigger Generator (PTG) Module ....339 Symbols Used in Opcode Descriptions..... 396 Pinout I/O Descriptions (table)..........28 Inter-Integrated Circuit (I C)..........275 Control Registers ............278 Resources..............277  2011-2020 Microchip Technology Inc. DS70000657J-page 535...
  • Page 536 PIC24EPXXXGP/MC203 Devices)..... 90 ECAN1 (When WIN (C1CTRL1) = 0 or 1) for PPS Output (dsPIC33EPXXXGP/MC204/504, dsPIC33EPXXXMC/GP50X Devices ....87 PIC24EPXXXGP/MC204 Devices)..... 91 ECAN1 (When WIN (C1CTRL1) = 0) for dsPIC33EPXXXMC/GP50X Devices ....87  2011-2020 Microchip Technology Inc. DS70000657J-page 536...
  • Page 537 INT1HLDL (Interval 1 Timer Hold Low Word)... 266 CxFEN1 (ECANx Acceptance Filter Enable 1) ..302 INT1TMRH (Interval 1 Timer High Word) ....265 CxFIFO (ECANx FIFO Status)........296 INT1TMRL (Interval 1 Timer Low Word) ....265  2011-2020 Microchip Technology Inc. DS70000657J-page 537...
  • Page 538 Special Features of the CPU ..........381 High Word)............263 QEI1LECL (QEI1 Less Than or Equal Compare Control Registers ............270 Low Word)............263 Helpful Tips............... 269 QEI1STAT (QEI1 Status) .......... 258 Resources ..............269  2011-2020 Microchip Technology Inc. DS70000657J-page 538...
  • Page 539 WWW Address ..............540 SPI1 Master Mode (Half-Duplex, WWW, On-Line Support ............. 25 Transmit Only, CKE = 1)........445 SPI1 Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) ........... 454  2011-2020 Microchip Technology Inc. DS70000657J-page 539...
  • Page 540 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 540...
  • Page 541: The Microchip Website

    To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2011-2020 Microchip Technology Inc. DS70000657J-page 541...
  • Page 542 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 542...
  • Page 543: Product Identification System

    = Plastic Shrink Small Outline - (28-pin) 5.30 mm body (SSOP) = Very Thin Leadless Array - (36-pin) 5x5 mm body (VTLA) = Very Thin Leadless Array - (44-pin) 6x6 mm body (VTLA)  2011-2020 Microchip Technology Inc. DS70000657J-page 543...
  • Page 544 AND PIC24EPXXXGP/MC20X NOTES:  2011-2020 Microchip Technology Inc. DS70000657J-page 544...
  • Page 545 Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies.
  • Page 546 New York, NY Tel: 46-31-704-60-40 Tel: 631-435-6000 Sweden - Stockholm San Jose, CA Tel: 46-8-5090-4654 Tel: 408-735-9110 UK - Wokingham Tel: 408-436-4270 Tel: 44-118-921-5800 Canada - Toronto Fax: 44-118-921-5820 Tel: 905-695-1980 Fax: 905-695-2078  2011-2020 Microchip Technology Inc. DS70000657J-page 546 02/28/20...

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