Figure 3-2. Pipeline Diagram Of The Issue If There Is A Stall In The E3 Slot Of The Instruction I1 - Texas Instruments TMS320F2807 Series Instruction Manual

Real-time mcus silicon errata silicon revisions c, b
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Silicon Revision C Usage Notes and Advisories
Advisory (continued) FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation
Figure 3-2
instruction I1.
Workarounds
Treat MPYF32, ADDF32, SUBF32, and MACF32 in this scenario as 3p-cycle instructions.
Three NOPs or non-conflicting instructions must be placed in the delay slot of the
instruction.
The C28x Code Generation Tools v.6.2.0 and later will both generate the correct
instruction sequence and detect the error in assembly code. In previous versions, v6.0.5
(for the 6.0.x branch) and v.6.1.2 (for the 6.1.x branch), the compiler will generate the
correct instruction sequence but the assembler will not detect the error in assembly code.
Example of Workaround:
|| MOV32 *XAR7++, R4H
|| MOV32 *--SP, R2H
Figure 3-3
20
TMS320F2807x Real-Time MCUs Silicon Errata
Silicon Revisions C, B
shows the pipeline diagram of the issue if there is a stall in the E3 slot of the
Instruction
MPYF32 R6H, R5H, R0H
I1
|| MOV32 *XAR7++, R4H
I2
F32TOUI16R R3H, R4H
ADDF32 R3H, R2H, R0H
I3
|| MOV32 *--SP, R2H
I4
MOV32 @XAR3, R6H
Figure 3-2. Pipeline Diagram of the Issue if There is a Stall in the E3 Slot of the
MPYF32 R6H, R5H, R0H
F32TOUI16R R3H, R4H
ADDF32 R2H, R2H, R0H
NOP
MOV32 @XAR3, R6H
shows the pipeline diagram with the workaround in place.
Copyright © 2023 Texas Instruments Incorporated
F1
F2
D1
D2
R1
R2
E
W
FPU pipeline-->
R1
R2
E1
E2
I1
I2
I1
I3
I2
I1
I4
I3
I2
I1
I4
I3
I2
I1
I4
I3
I2
I1
I4
I3
I2
I1
I4
I3
I2
I1
I4
I3
I2
I4
I3
I2
I4
I3
Instruction I1
; 3p FPU instruction that writes to R6H
; delay slot
; delay slot
; alignment cycle
; FPU register read of R6H
SPRZ423J – OCTOBER 2014 – REVISED MARCH 2023
www.ti.com
Comments
E3
I4 samples the result as it enters
the R2 phase, but I1 is stalled in
E3 and is unable to forward the
I1
product of R5H*R0H to I4 (R6H does
(STALL)
not have the product yet due to a
design bug). So, I4 reads the old
value of R6H.
There is no change in the pipeline
as it was stalled in the previous
I1
cycle. I4 had already sampled the
old value of R6H in the previous
cycle.
I2
Stall over
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