Video Fifo - Analog Devices Advantiv ADV7619 Hardware User's Manual

UG-237
Function
BG_DEEP_COLOR_MODE[1:0]
00 (default)
01
10
11

VIDEO FIFO

The ADV7619 contains a FIFO located between the incoming TMDS data and the CP core (refer to Figure 10). Data arriving over the
HDMI link will be at 1X for non-deep color mode (8 bits per channel), and 1.25X, 1.5X, or 2X for deep color modes (30, 36, and 48 bits,
respectively). Data unpacking and data rate reduction must be performed on the incoming HDMI data to provide the CP core with the
correct data rate and data bit width. The video FIFO is used to pass data safely across the clock domains.
The video FIFO also provides extreme robustness to jitter on the TMDS clock. The CP clock is generated by a DPLL running on the
incoming TMDS clock, and the CP clock may contain less jitter than the incoming TMDS clock. The video FIFO provides immunity to
the incoming jitter and the resultant clock phase mismatch between the CP clock and the TMDS clock.
TMDS
CLOCK
TMDS
CHANNEL 0
TMDS
CHANNEL 1
TMDS
CHANNEL 2
The video FIFO is designed to operate completely autonomously. It automatically resynchronizes the read and write pointers if they are
about to point to the same location. However, it is also possible for the user to observe and control the FIFO operation with a number of
FIFO status and control registers.
For video with pixel clock above 170 MHz DPLL must be bypassed, in that FIFO is clocked by 1x TMDS PLL clock.
DCFIFO_LEVEL[2:0] , Addr 68 (HDMI), Address 0x1C[2:0] (Read Only)
A readback that indicates the distance between the read and write pointers. Overflow/underflow would read as Level 0. Ideal centered
functionality would read as 0b100.
Function
DCFIFO_LEVEL[2:0]
000 (default)
001
010
011
100
101
110
111
DCFIFO_LOCKED , Addr 68 (HDMI), Address 0x1C[3] (Read Only)
A readback to indicate if video FIFO is locked.
Description
8-bit color per channel
10-bit color per channel
12-bit color per channel
16-bit color per channel (not supported)
TMDS
PLL
TMDS CH0
10
TMDS
SAMPLING
TMDS CH1
AND
DATA
10
RECOVERY
TMDS CH2
10
Figure 10. HDMI Video FIFO
Description
FIFO has underflowed or overflowed.
FIFO is about to overflow.
FIFO has some margin.
FIFO has some margin.
FIFO perfectly balanced
FIFO has some margin.
FIFO has some margin.
FIFO is about to underflow.
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DIVIDER
R
12
G
12
B
TMDS
12
DECODING
HS
VS
DE
Hardware User Guide
DPLL
R
12
G
12
B
FIFO
12
HS
VS
DE