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Table 11-2. MMCRO Bit Settings (Continued)
Bit
Name
Description
7-8
RTCSELECT
64-bit time base, bit selection enable
00
Pick bit 63 to count
01
Pick bit 55 to count
10
Pick bit 51 to count
11
Pick bit 47 to count
9
INTONBITTRANS
Causes interrupt signaling on bit transition (identified in RTCSELECT) from off to on.
0
Do not allow interrupt signal on the transition of a chosen bit.
1
Signal interrupt on the transition of a chosen bit.
Software is responsible for setting and clearing INTONBITTRANS.
10-15 THRESHOLD
Threshold value. All 6 bits are supported by the MPC750; allowing threshold values
from 0 to 63. The intent of the THRESHOLD support is to characterize L 1 data cache
misses.
16
PMC11NTCONTROL Enables interrupt signaling due to PMC1 counter overflow.
0
Disable PMC1 interrupt signaling due to PMC1 counter overflow.
1
Enable PMC1 Interrupt signaling due to PMC1 counter overflow.
17
PMCINTCONTROL
Enable interrupt signaling due to any PMC2-PMC4 counter overflow. Overrides the
setting of DISCOUNT.
0
Disable PMC2-PMC4 interrupt signaling due to PMC2-PMC4 counter overflow.
1
Enable PMC2-PMC4 interrupt signaling due to PMC2-PMC4 counter overflow.
18
PMCTRIGGER
Can be used to trigger counting of PMC2-PMC4 after PMC1 has overflowed or after a
performance monitor interrupt is signaled.
0
Enable PMC2-PMC4 counting.
1
Disable PMC2-PMC4 counting until either PMC1 [0)
=
1 or a performance monitor
interrupt is signaled.
19-25 PMC1SELECT
PMC1 input selector, 128 events selectable; 25 defined. See Table 11-5.
26-31
PMC2SELECT
PMC2 input selector, 64 events selectable; 21 defined. See Table 11-6.
MMCRO can be accessed with the mtspr and mfspr instructions using SPR 952.
11.2.1.2 User Monitor Mode Control Register 0 (UMMCRO)
The contents of MMCRO are reflected to UMMCRO, which can be read
by
user-level
software. UMMCRO can be accessed with the mfspr instructions using SPR 936.
11.2.1.3 Monitor Mode Control Register 1 (MMCR1)
The monitor mode control register 1 (MMCRl) functions as an event selector for
performance monitor counter registers 3 and 4 (PMC3 and PMC4). The MMCRI register
is shown in Figure 11-2.
o
4 5
9 10
31
Figure 11-2. Monitor Mode Control Register 1 (MMCR1)
Chapter 11. Performance Monitor
11-5
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