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When the MPC750 is not the address bus master, GBL is an input. The MPC750 snoops a
transaction if TS and GBL are asserted together in the same bus clock cycle (this is a
qualified snooping condition). No snoop update to the MPC750 cache occurs if the snooped
transaction is not marked global. This includes invalidation cycles.
When the MPC750 detects a qualified snoop condition, the address associated with the TS
is compared against the data cache tags. Snooping completes if no hit is detected. If,
however, the address hits in the cache, the MPC750 reacts according to the MEl protocol
shown in Figure 8-14, assuming the WIM bits are set to write-back, caching-allowed, and
coherency-enforced modes (WIM
=
001).
SH =Snoop Hit
RH =Read Hit
WH =Write Hit
WM=Write Miss
RM =Read Miss
BUS TRANSACTIONS
(]) = Snoop Push
CD= Cache Line Fill
SH/CRW=Snoop Hit, Cacheable ReadIWrite
SH/CIR =Snoop Hit, Caching-Inhibited Read
Figure 8-14. MEl Cache Coherency Protocol-State Diagram (WIM = 001)
Chapter 8. System Interface Operation
8-27
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