Motorola MPC750 User Manual page 412

Table A-26. Processor Control Instructions
Name 0 5 6 7 8 9 1011 12131415161718192021 22232425262728293031
merxr 31 crtS 512
o
mfer 31 D
19
mfmsr
1
31 D 83
mfspr
2
31
D 339
r-------+---------,r------------------~--------------------,r4
mftb 31 D
mterf
mtmsr
1,3
mtmsrd
1,4
mtspr
2
31 S
31 S
31 S
31 D
Notes:
1
Supervisor-level instruction
2
Supervisor- and user-level instruction
3
Optional 64-bit bridge instruction
4
64-bit instruction
spr
Table A-27. Cache Management Instructions
371
144
146
178
467
Name
0
5 6 7 8 9 1011 12131415161718192021 22232425262728293031
deba 1,3
debf
debi
2
debst
debt
debtst
debz
iebi
31 A B
31 A B
31
A
B
31
A B
31
· · . , · , · , • . , . . 'pip,(
~O'i.
A B
31
A B
31 A B
31
A
B
Notes:
1
Optional instruction
2
Supervisor-level instruction
3
32-bit instruction not implemented by the MPC750
Appendix A. PowerPC Instruction Set Listings
758
86
0,
470
54
~
....
278
10
246
10
1014
1
0
982
1
0
A-27