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1.8.1 PowerPC Memory Management Model
The primary functions of the MMU are to translate logical (effective) addresses to physical
addresses for memory accesses and to provide access protection on blocks and pages of
memory. There are two types of accesses generated by the MPC750 that require address
translation-instruction accesses, and data accesses to memory generated by load, store,
and cache control instructions.
The PowerPC architecture defines different resources for 32- and 64-bit processors; the
MPC750 implements the 32-bit memory management model. The memory-management
model provides 4 Gbytes of logical address space accessible to supervisor and user
programs with a 4-Kbyte page size and 256-Mbyte segment size. BAT block sizes range
from 128 Kbyte to 256 Mbyte and are software selectable. In addition, it defines an interim
52-bit virtual address and hashed page tables for generating 32-bit physical addresses.
The architecture also provides independent four-entry BAT arrays for instructions and data
that maintain address translations for blocks of memory. These entries define blocks that
can vary from 128 Kbytes to 256 Mbytes. The BAT arrays are maintained by system
software.
The PowerPC MMU and exception model support demand-paged virtual memory. Virtual
memory management permits execution of programs larger than the size of physical
memory; demand-paged implies that individual pages are loaded into physical memory
from system memory only when they are first accessed by an executing program.
The hashed page table is a variable-sized data structure that defines the mapping between
virtual page numbers and physical page numbers. The page table size is a power of 2, and
its starting address is a multiple of its size. The page table contains a number of page table
entry groups (PTEGs). A PTEG contains eight page table entries (PTEs) of eight bytes
each; therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for table
search operations.
Setting MSR[IR] enables instruction address translations and MSR[DR] enables data
address translations. If the bit is cleared, the respective effective address is the same as the
physical address.
1.8.2 MPC750 Microprocessor Memory Management Implementation
The MPC750 implements separate MMUs for instructions and data.
It
implements a copy
of the segment registers in the instruction MMU, however, read and write accesses (mfsr
and mtsr) are handled through the segment registers implemented as part of the data MMU.
The MPC750 MMU is described in Section 1.2.3, "Memory Management Units (MMUs)."
The R (referenced) bit is updated in the PTE in memory (if necessary) during a table search
due to a TLB miss. Updates to the C (changed) bit are treated like TLB misses. A complete
table search is performed and the entire TLB entry is rewritten to update the C bit.
Chapter 1. Overview
1-33
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