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Bar over signal name indicates active low
MPC750 input (while MPC750 is a bus master)
MPC750 output (while MPC750 is a bus master)
MPC750 output (grouped: here, address plus attributes) :
MPC750 internal signal (inaccessible to the user, but:
used in diagrams to clarify operations)
Compelling dependency-event will occur on the
next clock cycle
Prerequisite dependency-event will occur on an
undetermined subsequent clock cycle
MPC750 three-state output or input
MPC750 nonsampled input
Signal with sample point
A sampled condition (dot on high or low state)
with multiple dependencies
Timing for a signal had it been asserted (it is not
actually asserted)
Figure 8-2. Timing Diagram Legend
8.2 Memory Access Protocol
Memory accesses are divided into address and data tenures. Each tenure has three phases-
bus arbitration, transfer, and termination. The MPC750 also supports address-only
transactions. Note that address and data tenures can overlap, as shown in Figure 8-3.
Figure 8-3 shows that the address and data tenures are distinct from one another and that
both consist of three phases-arbitration, transfer, and termination. Address and data
tenures are independent (indicated in Figure 8-3 by the fact that the data tenure begins
before the address tenure ends), which allows split-bus transactions to be implemented at
the system level in multiprocessor systems. Figure 8-3 shows a data transfer that consists
of a single-beat transfer of as many as 64 bits. Four-beat burst transfers of 32-byte cache
lines require data transfer termination signals for each beat of data.
8-6
MPC750 RISC Microprocessor User's Manual
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